CN1956180B - Substrate structure of electronic device packed by liquid resin drip - Google Patents
Substrate structure of electronic device packed by liquid resin drip Download PDFInfo
- Publication number
- CN1956180B CN1956180B CN2006101088852A CN200610108885A CN1956180B CN 1956180 B CN1956180 B CN 1956180B CN 2006101088852 A CN2006101088852 A CN 2006101088852A CN 200610108885 A CN200610108885 A CN 200610108885A CN 1956180 B CN1956180 B CN 1956180B
- Authority
- CN
- China
- Prior art keywords
- substrate body
- electronic device
- liquid resin
- substrate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
A substrate structure of electronic component packaged by liquid spot-gluing resin consists of substrate body, exposed object packaged on substrate body and metal printed circuit on substrate body. It is featured as setting tin solder escaping metal plate and soldering paste escaping space separately at preset package region on said substrate body.
Description
The application is that the applicant submitted on March 26th, 2005, and application number is 200510033878.6, and invention and created name is the dividing an application of application for a patent for invention of liquid resin dropping packaging method.
[technical field]
The present invention relates to a kind of substrate, relate in particular to a kind of substrate structure of the electronic device of glue attitude resin-encapsulated that adopts.
[background technology]
Along with the needs of fields such as electronic communication to low-cost and miniaturization, require in the process for fabrication of semiconductor device process, employing was both simple and reliable as far as possible, can satisfy the technology of above-mentioned requirements again.On the electronic module substrate, want on as far as possible little area, directly realize the some glue attitude resin-encapsulated of semiconductor chip at low cost, liquid resinous scope control problem seems very outstanding.Resin flows on the zone, particularly miscellaneous part of not wishing to flow to, and not only can influence the electrical characteristics of entire circuit substrate, also can influence the substrate overall appearance, influences parts and replaces, and can't finish some expensive substrates modules are repaired.
[summary of the invention]
Technical problem to be solved by this invention is to provide a kind of substrate structure of electronic device of the employing point glue attitude resin-encapsulated that reduces hazard rate.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of substrate structure of the electronic device of glue attitude resin-encapsulated that adopts is provided, it comprises: the substrate body, be encapsulated into the operplate printing circuit on exposed object on this substrate body and this substrate body, the predetermined packed part on this substrate body is provided with solder paste escape space.
Described predetermined packed part also is provided with scolding tin escape metallic plate.
Should exposed object be one of semiconductor chip, conductive lead wire, pressure welding area electrode, extraction electrode, resistance, inductance, electric capacity or their combination.
The invention has the beneficial effects as follows:, thereby reduced the failure rate of product because the predetermined packed part of the present invention on the substrate body is provided with scolding tin escape metallic plate and solder paste escape space.
[description of drawings]
Fig. 1 is the vertical view of the some glue attitude resin-encapsulated of exposed object on the substrate body of the present invention.
Fig. 2 is along A-A ' sectional view shown in Figure 1.
Fig. 3 is the vertical view before the invention process encapsulation.
[embodiment]
See also Fig. 1 and Fig. 2, it is packed good to have shown among the figure at a slice substrate body 2 lastblocks, comprises the schematic diagram of the real dress parts of semiconductor chip in the liquid resin 4 and outside, the peripheral interface of resin.Can see in the vertical view by a square dam 6, the scope of liquid resin 4 is limited in that side of resin on dam 6.Its A-A ' sectional view has shown the exposed object 1 of liquid resin 4 inside, operplate printing circuit 3, conductive lead wire 7 and welding resistance lacquer 5.
The part that on substrate body 2, will be scheduled to encapsulate, design peripheral interface 12 with welding resistance lacquer 5, when adopting liquid resin 4 encapsulation to expose object 1, with the top of 4 glue of liquid resin at exposed object 1, cover exposed object 1 fully, liquid resin 4 is diffusion to the periphery, utilize the surface tension of the outer intermarginal generation at liquid resin 4 and peripheral interface 12, form the dam 6 stop liquid resin 4 excessive together, the amount of the liquid resin 4 by control point glue, make excessive power and this surface tension of liquid resin 4 keep balance, the liquid resin 4 of a glue can be limited in the encapsulation scope of our design.
Here be stressed that
A. stoping liquid resin 4 excessive dams 6 is that surface tension by liquid resin 4 and the outer intermarginal generation at peripheral interface 12 stops the excessive and dam that forms of liquid resin 4.
B. so-called some glue generally drops in 4 of liquid resins on the nudity body 1 exactly.Want the amount of the liquid resin 4 of control point glue, consider the surface tension of liquid resin 4, keep balance, just right.The amount of some glue is excessive, can make liquid resin 4 excessive to the dam 6 outside, cover and do not wish the part that encapsulates to influence the replacement of peripheral interface exterior part, repair again.
C. exposed object 1 can be semiconductor chip, conductive lead wire, pressure welding area electrode, extraction electrode, electronic device or their combination.
D. part or all of exposed object 1 is connected with operplate printing circuit 3.
E. after exposed object 1 was encapsulated in liquid resin 4 inside, heated substrate body 2 can solidify liquid resin 4.
Seeing also Fig. 3, is the vertical view before the invention process encapsulation.Scolding tin escape metallic plate 8 and solder paste escape space 9 have been designed in liquid resin 4 inside for this reason.Substrate body 2 connected by welding with being connected mainly of exposed object 1, in the resin that has solidified, consider that unnecessary scolding tin and solder paste have the place of an escape, in liquid resin dam 6, be provided with scolding tin escape metallic plate 8 and solder paste escape space 9 for this reason.
Because scolding tin escape metallic plate 8 and solder paste escape space 9 are arranged, can prevent in substrate body 2 heated processes that therefore the excessive outside to potting resin 4 of the unnecessary scolding tin and the solder paste of gasification is short-circuited with outside printed circuit 10 of resin or parts 11.By the setting in a kind of like this scolding tin escape metallic plate 8 and solder paste escape space 9, can improve a reliability of glue attitude resin-encapsulated.
The shape on dam 6 can be the shape of enclosed shape, also can be partially enclosed, the shape that part is open.Dam 6 shown in Fig. 1 is quadrangle dams of a sealing.
Claims (3)
1. one kind is adopted a substrate structure of the electronic device of glue attitude resin-encapsulated, it comprises: the substrate body, be encapsulated into the operplate printing circuit on exposed object on this substrate body and this substrate body, it is characterized in that: the predetermined packed part on this substrate body is provided with solder paste escape space.
2. the substrate structure of the electronic device of employing point glue attitude resin-encapsulated according to claim 1 is characterized in that: described predetermined packed part also is provided with scolding tin escape metallic plate.
3. the substrate structure of the electronic device of employing point glue attitude resin-encapsulated according to claim 1 is characterized in that: this exposed object is one of semiconductor chip, conductive lead wire, pressure welding area electrode, extraction electrode, resistance, inductance, electric capacity or their combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101088852A CN1956180B (en) | 2005-03-26 | 2005-03-26 | Substrate structure of electronic device packed by liquid resin drip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101088852A CN1956180B (en) | 2005-03-26 | 2005-03-26 | Substrate structure of electronic device packed by liquid resin drip |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100338786A Division CN100356532C (en) | 2005-03-26 | 2005-03-26 | Liquid resin dropping packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1956180A CN1956180A (en) | 2007-05-02 |
| CN1956180B true CN1956180B (en) | 2010-08-04 |
Family
ID=38063403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101088852A Expired - Fee Related CN1956180B (en) | 2005-03-26 | 2005-03-26 | Substrate structure of electronic device packed by liquid resin drip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1956180B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103402048A (en) * | 2013-07-30 | 2013-11-20 | 南昌欧菲光电技术有限公司 | Camera module, dust prevention and fixing method and installation method of camera module |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH619333A5 (en) * | 1977-11-01 | 1980-09-15 | Faselec Ag | Process for covering a flat component with a polymer |
| US5731547A (en) * | 1996-02-20 | 1998-03-24 | International Business Machines Corporation | Circuitized substrate with material containment means and method of making same |
| CN1246963A (en) * | 1997-02-10 | 2000-03-08 | 松下电子工业株式会社 | Resin sealed semiconductor device and method for manufacturing the same |
| CN1395302A (en) * | 2001-07-10 | 2003-02-05 | 北京握奇数据系统有限公司 | Chip packaging method and packaging method of its double-interface card |
| CN1507043A (en) * | 2002-12-06 | 2004-06-23 | 三菱电机株式会社 | Resin packaging semiconductor device |
-
2005
- 2005-03-26 CN CN2006101088852A patent/CN1956180B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH619333A5 (en) * | 1977-11-01 | 1980-09-15 | Faselec Ag | Process for covering a flat component with a polymer |
| US5731547A (en) * | 1996-02-20 | 1998-03-24 | International Business Machines Corporation | Circuitized substrate with material containment means and method of making same |
| CN1246963A (en) * | 1997-02-10 | 2000-03-08 | 松下电子工业株式会社 | Resin sealed semiconductor device and method for manufacturing the same |
| CN1395302A (en) * | 2001-07-10 | 2003-02-05 | 北京握奇数据系统有限公司 | Chip packaging method and packaging method of its double-interface card |
| CN1507043A (en) * | 2002-12-06 | 2004-06-23 | 三菱电机株式会社 | Resin packaging semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1956180A (en) | 2007-05-02 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100804 Termination date: 20130326 |