DE03024585T1 - Hochleistungsarchitektur für RISC-Mikroprozessor - Google Patents
Hochleistungsarchitektur für RISC-Mikroprozessor Download PDFInfo
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- DE03024585T1 DE03024585T1 DE0001385085T DE03024585T DE03024585T1 DE 03024585 T1 DE03024585 T1 DE 03024585T1 DE 0001385085 T DE0001385085 T DE 0001385085T DE 03024585 T DE03024585 T DE 03024585T DE 03024585 T1 DE03024585 T1 DE 03024585T1
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Classifications
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- G06F9/3822—Parallel decoding, e.g. parallel decode units
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Abstract
Superskalarer Mikroprozessor zum Verarbeiten von Befehlen, wobei der Mikroprozessor umfasst:
eine Befehlsabrufeinheit (102), die so konfiguriert ist, dass sie Befehle aus einem Befehlsspeicher (106) entsprechend einer sequentiellen Programmreihenfolge abruft;
einen Befehlspufferspeicher (264), der so geschaltet ist, dass er abgerufene Befehle von der Befehlsabrufeinheit (102) empfängt und so konfiguriert ist, dass er eine Vielzahl abgerufener Befehle gleichzeitig zur Ausführung verfügbar macht;
eine Vielzahl funktionaler Einheiten (478), die so konfiguriert sind, dass sie Befehle ausführen und damit Ergebnisdaten erzeugen;
eine Registerdatei (472), die eine Vielzahl von Einträgen enthält und so konfiguriert ist, dass sie Daten einschließlich der durch die Vielzahl funktionaler Einheiten (478) erzeugten Ergebnisdaten speichert, wobei jeder der Vielzahl von Einträgen durch Bezugnahme auf eine entsprechende Position in der Registerdatei zugänglich ist;
eine Decoderschaltung (490), die so konfiguriert ist, dass sie gleichzeitig Ausführungsressourcen für mehr als einen der Vielzahl verfügbaren Befehle in dem Befehlspufferspeicher identifiziert, wobei...
eine Befehlsabrufeinheit (102), die so konfiguriert ist, dass sie Befehle aus einem Befehlsspeicher (106) entsprechend einer sequentiellen Programmreihenfolge abruft;
einen Befehlspufferspeicher (264), der so geschaltet ist, dass er abgerufene Befehle von der Befehlsabrufeinheit (102) empfängt und so konfiguriert ist, dass er eine Vielzahl abgerufener Befehle gleichzeitig zur Ausführung verfügbar macht;
eine Vielzahl funktionaler Einheiten (478), die so konfiguriert sind, dass sie Befehle ausführen und damit Ergebnisdaten erzeugen;
eine Registerdatei (472), die eine Vielzahl von Einträgen enthält und so konfiguriert ist, dass sie Daten einschließlich der durch die Vielzahl funktionaler Einheiten (478) erzeugten Ergebnisdaten speichert, wobei jeder der Vielzahl von Einträgen durch Bezugnahme auf eine entsprechende Position in der Registerdatei zugänglich ist;
eine Decoderschaltung (490), die so konfiguriert ist, dass sie gleichzeitig Ausführungsressourcen für mehr als einen der Vielzahl verfügbaren Befehle in dem Befehlspufferspeicher identifiziert, wobei...
Claims (12)
- Superskalarer Mikroprozessor zum Verarbeiten von Befehlen, wobei der Mikroprozessor umfasst: eine Befehlsabrufeinheit (
102 ), die so konfiguriert ist, dass sie Befehle aus einem Befehlsspeicher (106 ) entsprechend einer sequentiellen Programmreihenfolge abruft; einen Befehlspufferspeicher (264 ), der so geschaltet ist, dass er abgerufene Befehle von der Befehlsabrufeinheit (102 ) empfängt und so konfiguriert ist, dass er eine Vielzahl abgerufener Befehle gleichzeitig zur Ausführung verfügbar macht; eine Vielzahl funktionaler Einheiten (478 ), die so konfiguriert sind, dass sie Befehle ausführen und damit Ergebnisdaten erzeugen; eine Registerdatei (472 ), die eine Vielzahl von Einträgen enthält und so konfiguriert ist, dass sie Daten einschließlich der durch die Vielzahl funktionaler Einheiten (478 ) erzeugten Ergebnisdaten speichert, wobei jeder der Vielzahl von Einträgen durch Bezugnahme auf eine entsprechende Position in der Registerdatei zugänglich ist; eine Decoderschaltung (490 ), die so konfiguriert ist, dass sie gleichzeitig Ausführungsressourcen für mehr als einen der Vielzahl verfügbaren Befehle in dem Befehlspufferspeicher identifiziert, wobei die identifizierten Ausführungsressourcen für jeden der verfügbaren Befehle eine funktionale Einheit, die in der Lage ist, den Befehl auszuführen, und einen Registerdateieintrag entsprechend einer Quelle eines Operanden für den Befehl enthalten; eine Ausgabesteuerschaltung (498 ), die an die Decoderschaltung (490 ) geschaltet und so konfiguriert ist, dass sie gleichzeitig mehr als einen der Befehle aus dem Befehlspufferspeicher an die funktionalen Einheiten zur Ausführung auf Basis der Verfügbarkeit der durch die Decoderschaltung (490 ) identifizierten Ausführungsressourcen und ohne Berücksichtigung der sequentiellen Programmreihenfolge ausgibt; eine Vielzahl von Datenleitwegen (588 ), die zwischen die Vielzahl funktionaler Einheiten und die Registerdatei geschaltet und so konfiguriert sind, dass sie gleichzeitig Ergebnisdaten von mehr als einer der Vielzahl funktionaler Einheiten (478 ) zu der Registerdatei (472 ) übertragen; eine Umgehungs-Steuerlogik (626 ,694 ), die mit der Vielzahl von Datenleitwegen verbunden und so konfiguriert ist, dass sie Ergebnisdaten von einer ersten der Vielzahl funktionaler Einheiten als Operanden-Daten für eine oder mehrere andere der Vielzahl funktionaler Einheiten über einen alternativen Datenweg zuführt, der die Registerdatei umgeht, wobei das Zuführen von Ergebnisdaten über den alternativen Datenweg gleichzeitig zum Übertragen von Ergebnisdaten zu der Registerdatei stattfindet; und eine Ausscheide-Steuerlogik (500 ), die an die Registerdatei geschaltet und so konfiguriert ist, dass sie gleichzeitig eine Vielzahl von Befehlen entsprechend der sequentiellen Programmreihenfolge ausscheidet. - Mikroprozessor nach Anspruch 1, wobei: die Vielzahl funktionaler Einheiten eine funktionale Ganzzahl-Einheit (
640 ,642 ,644 ) und eine funktionale Gleitkomma-Einheit (712 ,714 ,716 ) enthält; und die Umgehungs-Steuerlogik des Weiteren so konfiguriert ist, dass ein Ganzzahl-Ergebnis von der funktionalen Ganzzahl-Einheit über den alternativen Datenweg (628 ) zu der funktionalen Gleitkomma-Einheit (712 ,714 ,716 ) überfragen wird. - Mikroprozessor nach Anspruch 1, wobei: die Vielzahl funktionaler Einheiten eine funktionale Ganzzahl-Einheit (
640 ,642 ,644 ) und eine funktionale Gleitkomma-Einheit (712 ,714 ,716 ) enthält; und die Umgehungs-Steuerlogik des Weiteren so konfiguriert ist, dass ein Gleitkomma-Ergebnis von der funktionalen Gleitkomma-Einheit (712 ,714 ,716 ) über den alternativen Datenweg (636 ) zu der funktionalen Ganzzahl-Einheit (640 ,642 ,644 ) übertragen wird. - Mikroprozessor nach Anspruch 1, der des Weiteren umfasst: Operanden-Datenleitwege (
480 ), die zwischen die Registerdatei und die funktionalen Einheiten geschaltet und so konfiguriert sind, dass sie gleichzeitig Operanden-Daten zu mehr als einer der funktionalen Einheiten übertragen. - Mikroprozessor nach Anspruch 4, wobei die Operanden-Datenleitwege (
480 ) Operanden-Daten direkt von der Registerdatei zu den funktionalen Einheiten übertragen. - Mikroprozessor nach Anspruch 1, wobei die Registerdatei enthält: einen Temporär-Pufferspeicher (
552 ) mit einer ersten Vielzahl von Einträgen; und eine Ausscheide-Registeranordnung (554 ) mit einer zweiten Vielzahl von Einträgen, wobei die Ausscheide-Steuerlogik des Weiteren so konfiguriert ist, dass, wenn ein Befehl ausgeschieden wird, entsprechende Ergebnisdaten von dem Temporär-Pufferspeicher (552 ) zu der Ausscheide-Registeranordnung (554 ) übertragen werden. - Verfahren zum Bearbeiten von Befehlen in einem superskalaren Mikroprozessor, wobei das Verfahren umfasst: Abrufen von Befehlen aus einem Befehlsspeicher (
106 ) entsprechend einer sequentiellen Programmreihenfolge; gleichzeitiges Verfügbarmachen einer Vielzahl abgerufener Befehle in einem Befehlspufferspeicher (264 ) zur Ausführung; gleichzeitiges Identifizieren von Ausführungsressourcen für mehr als einen der Vielzahl verfügbarer Befehle in dem Befehlspufferspeicher (472 ), wobei die identifizierten Ausführungsressourcen für jeden der mehr als einen der Vielzahl verfügbarer Befehle eine funktionale Einheit (478 ), die in der Lage ist, den Befehl auszuführen, und einen Registerdateieintrag entsprechend einer Quelle eines Operanden für den Befehl enthalten; gleichzeitiges Ausgeben mehr als eines der Vielzahl verfügbarer Befehle aus dem Befehlspufferspeicher (264 ) zur Ausführung durch eine Vielzahl funktionaler Einheiten (478 ) auf Basis der Verfügbarkeit der identifizierten Ausführungsressourcen für jeden Befehl und ohne Berücksichtung der sequentiellen Programmreihenfolge; Ausführen der ausgegebenen Befehle in der Vielzahl funktionaler Einheiten (478 ), um so Ergebnisdaten zu erzeugen; Übertragen der Ergebnisdaten von den funktionalen Einheiten zu einer Registerdatei (472 ), wobei die Registerdatei eine Vielzahl von Einträgen enthält und jeder der Vielzahl von Einträgen durch Bezugnahme auf eine entsprechende Position in der Registerdatei zugänglich ist; gleichzeitig zu dem Vorgang des Übertragens Verteilen der Ergebnisdaten von einer ersten der Vielzahl funktionaler Einheiten als Operanden-Daten für eine oder mehrere der Vielzahl funktionaler Einheiten über einen Umgehungs-Datenweg (628 ,636 ), der die Registerdatei umgeht; und Ausscheiden von Befehlen entsprechend der sequentiellen Programmreihenfolge. - Verfahren nach Anspruch 7, wobei: die Vielzahl funktionaler Einheiten (
478 ) eine funktionale Ganzzahl-Einheit (640 ,642 ,644 ) und eine funktionale Gleitkomma-Einheit (712 ,714 ,716 ) enthält; und das Zuführen der Ergebnisdaten das Zuführen von Ergebnisdaten von der funktionalen Ganzzahl-Einheit zu der funktionalen Gleitkomma-Einheit über den Umgehungs-Datenweg (628 ) einschließt. - Verfahren nach Anspruch 7, wobei: die Vielzahl funktionaler Einheiten eine funktionale Ganzzahl-Einheit (
640 ,642 ,644 ) und eine funktionale Gleitkomma-Einheit (712 ,714 ,716 ) enthält; und das Zuführen der Ergebnisdaten das Zuführen von Ergebnisdaten von der funktionalen Gleitkomma-Einheit zu der funktionalen Ganzzahl-Einheit über den Umgehungs-Datenweg (636 ) einschließt. - Verfahren nach Anspruch 7, das des Weiteren umfasst: gleichzeitiges Übertragen von Operanden-Daten von der Registerdatei zu mehr als einer der funktionalen Einheiten über eine Vielzahl von Operanden-Datenleitwegen (
480 ). - Verfahren nach Anspruch 10, wobei die Operanden-Datenleitwege Operanden-Daten direkt von der Registerdatei (
472 ) zu den funktionalen Einheiten (478 ) übertragen. - Verfahren nach Anspruch 7, wobei die Registerdatei enthält: einen Temporär-Zwischenspeicher (
552 ) mit einer ersten Vielzahl an Einträgen; und eine Ausscheide-Registeranordnung (554 ) mit einer zweiten Vielzahl von Einträgen, wobei das Ausscheiden eines Befehls das Übertragen entsprechender Ergebnisdaten von dem Temporär-Pufferspeicher (552 ) zu der Ausscheide-Registeranordnung (554 ) einschließt.
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US727006 | 1991-07-08 |
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DE0001385085T Pending DE03024585T1 (de) | 1991-07-08 | 1992-07-07 | Hochleistungsarchitektur für RISC-Mikroprozessor |
DE69232113T Expired - Lifetime DE69232113T2 (de) | 1991-07-08 | 1992-07-07 | Hochleistungsarchitektur für risc-mikroprozessor |
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DE69232113T Expired - Lifetime DE69232113T2 (de) | 1991-07-08 | 1992-07-07 | Hochleistungsarchitektur für risc-mikroprozessor |
DE69233777T Expired - Lifetime DE69233777D1 (de) | 1991-07-08 | 1992-07-07 | Hochleistungsarchitektur für RISC-Mikroprozessor |
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EP (3) | EP1385085B1 (de) |
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AT (3) | ATE206829T1 (de) |
DE (4) | DE69233313T2 (de) |
HK (2) | HK1014782A1 (de) |
WO (1) | WO1993001545A1 (de) |
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