DE10196702T1 - Verfahren und Einrichtung für eine skalierbare, eindeutig gemachte Kohärenz in gemeinsam benutzten Speicherhierarchien - Google Patents

Verfahren und Einrichtung für eine skalierbare, eindeutig gemachte Kohärenz in gemeinsam benutzten Speicherhierarchien

Info

Publication number
DE10196702T1
DE10196702T1 DE10196702T DE10196702T DE10196702T1 DE 10196702 T1 DE10196702 T1 DE 10196702T1 DE 10196702 T DE10196702 T DE 10196702T DE 10196702 T DE10196702 T DE 10196702T DE 10196702 T1 DE10196702 T1 DE 10196702T1
Authority
DE
Germany
Prior art keywords
coherence
scalable
shared memory
memory hierarchies
unambiguously
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10196702T
Other languages
English (en)
Inventor
Hang Nguyen
Quinn Merrell
Sujat Jamil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10196702T1 publication Critical patent/DE10196702T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
DE10196702T 2000-09-29 2001-09-26 Verfahren und Einrichtung für eine skalierbare, eindeutig gemachte Kohärenz in gemeinsam benutzten Speicherhierarchien Withdrawn DE10196702T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/677,122 US6651145B1 (en) 2000-09-29 2000-09-29 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
PCT/US2001/030359 WO2002027497A2 (en) 2000-09-29 2001-09-26 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies

Publications (1)

Publication Number Publication Date
DE10196702T1 true DE10196702T1 (de) 2003-08-28

Family

ID=24717419

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196702T Withdrawn DE10196702T1 (de) 2000-09-29 2001-09-26 Verfahren und Einrichtung für eine skalierbare, eindeutig gemachte Kohärenz in gemeinsam benutzten Speicherhierarchien

Country Status (7)

Country Link
US (2) US6651145B1 (de)
CN (1) CN1277216C (de)
AU (1) AU2001296370A1 (de)
DE (1) DE10196702T1 (de)
GB (1) GB2384344B (de)
HK (1) HK1054808A1 (de)
WO (1) WO2002027497A2 (de)

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US7430569B2 (en) * 2002-11-27 2008-09-30 Sap Ag Computerized replication of data objects
US7464091B2 (en) * 2002-11-27 2008-12-09 Sap Ag Method and software for processing data objects in business applications
US7225302B2 (en) * 2002-11-27 2007-05-29 Sap Ag Method and software application for avoiding data loss
US7409412B2 (en) * 2002-11-27 2008-08-05 Sap Ag Data element and structure for data processing
US20040111563A1 (en) * 2002-12-10 2004-06-10 Edirisooriya Samantha J. Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
US8533401B2 (en) * 2002-12-30 2013-09-10 Intel Corporation Implementing direct access caches in coherent multiprocessors
US7082500B2 (en) * 2003-02-18 2006-07-25 Cray, Inc. Optimized high bandwidth cache coherence mechanism
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20050204102A1 (en) * 2004-03-11 2005-09-15 Taylor Richard D. Register access protocol for multi processor systems
US7610200B2 (en) * 2004-08-30 2009-10-27 Lsi Corporation System and method for controlling sound data
TWI277872B (en) * 2004-10-19 2007-04-01 Via Tech Inc Method and related apparatus for internal data accessing of computer system
DE102004055013A1 (de) * 2004-11-15 2006-05-24 Infineon Technologies Ag Computereinrichtung
US7804504B1 (en) 2004-12-13 2010-09-28 Massachusetts Institute Of Technology Managing yield for a parallel processing integrated circuit
US7624236B2 (en) * 2004-12-27 2009-11-24 Intel Corporation Predictive early write-back of owned cache blocks in a shared memory computer system
US20060143397A1 (en) * 2004-12-29 2006-06-29 O'bleness R F Dirty line hint array for cache flushing
US8010498B2 (en) 2005-04-08 2011-08-30 Microsoft Corporation Virtually infinite reliable storage across multiple storage devices and storage services
US20070028064A1 (en) * 2005-07-28 2007-02-01 Mcbrearty Gerald F Method for suspending mirrored writes during large data transfers
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US20080077638A1 (en) * 2006-09-21 2008-03-27 Microsoft Corporation Distributed storage in a computing environment
US7853754B1 (en) 2006-09-29 2010-12-14 Tilera Corporation Caching in multicore and multiprocessor architectures
US9122617B2 (en) * 2008-11-21 2015-09-01 International Business Machines Corporation Pseudo cache memory in a multi-core processor (MCP)
US7804329B2 (en) * 2008-11-21 2010-09-28 International Business Machines Corporation Internal charge transfer for circuits
US9886389B2 (en) * 2008-11-21 2018-02-06 International Business Machines Corporation Cache memory bypass in a multi-core processor (MCP)
US9824008B2 (en) * 2008-11-21 2017-11-21 International Business Machines Corporation Cache memory sharing in a multi-core processor (MCP)
US8806129B2 (en) * 2008-11-21 2014-08-12 International Business Machines Corporation Mounted cache memory in a multi-core processor (MCP)
US8347050B2 (en) * 2009-01-27 2013-01-01 Microsoft Corporation Append-based shared persistent storage
US8799572B2 (en) 2009-04-20 2014-08-05 Microsoft Corporation Sliding-window multi-class striping
JP5568939B2 (ja) * 2009-10-08 2014-08-13 富士通株式会社 演算処理装置及び制御方法
US9477600B2 (en) 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
US8688914B2 (en) 2011-11-01 2014-04-01 International Business Machines Corporation Promotion of partial data segments in flash cache
US9529532B2 (en) 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US9372800B2 (en) * 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US10592459B2 (en) 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
CN105426319B (zh) * 2014-08-19 2019-01-11 超威半导体产品（中国）有限公司 动态缓存分区设备和方法
CN107643991B (zh) * 2017-09-22 2023-09-19 北京算能科技有限公司 数据处理芯片和系统、数据存储转发处理方法
CN109614220B (zh) 2018-10-26 2020-06-30 阿里巴巴集团控股有限公司 一种多核系统处理器和数据更新方法
CN117093511A (zh) * 2023-09-04 2023-11-21 海光云芯集成电路设计(上海)有限公司 访存控制方法、访存控制装置、芯片及电子设备

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JPH0625984B2 (ja) * 1990-02-20 1994-04-06 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン マルチプロセツサ・システム
JP3009430B2 (ja) * 1990-07-09 2000-02-14 キヤノン株式会社 プロセッサおよびそのキャッシュメモリ制御方法
US5524212A (en) * 1992-04-27 1996-06-04 University Of Washington Multiprocessor system with write generate method for updating cache
US5680576A (en) * 1995-05-05 1997-10-21 Silicon Graphics, Inc. Directory-based coherence protocol allowing efficient dropping of clean-exclusive data
JPH0950400A (ja) * 1995-08-10 1997-02-18 Nec Corp マルチプロセッサシステム

Also Published As

Publication number Publication date
US6651145B1 (en) 2003-11-18
GB0309110D0 (en) 2003-05-28
US7003632B2 (en) 2006-02-21
AU2001296370A1 (en) 2002-04-08
US20030233523A1 (en) 2003-12-18
WO2002027497A2 (en) 2002-04-04
CN1277216C (zh) 2006-09-27
GB2384344B (en) 2004-12-29
HK1054808A1 (en) 2003-12-12
GB2384344A (en) 2003-07-23
CN1474969A (zh) 2004-02-11
WO2002027497A3 (en) 2003-01-30

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