DE102012013136A1 - Method for improving reproducibility of high levels of current gain of e.g. NPN transistor, in semiconductor switching circuit, involves producing exposing and corroding during polysilicon separating and photolithographic processes of gate - Google Patents

Method for improving reproducibility of high levels of current gain of e.g. NPN transistor, in semiconductor switching circuit, involves producing exposing and corroding during polysilicon separating and photolithographic processes of gate Download PDF

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DE102012013136A1
DE102012013136A1 DE201210013136 DE102012013136A DE102012013136A1 DE 102012013136 A1 DE102012013136 A1 DE 102012013136A1 DE 201210013136 DE201210013136 DE 201210013136 DE 102012013136 A DE102012013136 A DE 102012013136A DE 102012013136 A1 DE102012013136 A1 DE 102012013136A1
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polysilicon
gate
ring
polysilicon gate
current gain
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DE102012013136B4 (en
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Klaus Gille
Tibor Kerekes
Hagen Wald
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X Fab Semiconductor Foundries GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Abstract

The method involves producing a supplementary polysilicon ring (4) with certain constant distance to a polysilicon gate (2) concentric around a drain that is functioned as an internal collector terminal (3) of a collector. The supplementary polysilicon ring is connected with the polysilicon gate over a polysilicon bridge, where edge distance of the polysilicon ring is one to two times greater than width of edge of the polysilicon gate. Exposing and corroding are produced during process steps such as polysilicon separating and photolithographic process of the polysilicon gate when coating.

Description

Die Erfindung betrifft ein Verfahren zur Herstellung eines in einem CMOS-Schaltkreis integrierten, als lateraler Bipolar-Transistor betriebenen MOS-Transistors mit hoher Stromverstärkung, basierend auf der Triple-Well-CMOS-Technologie.The invention relates to a method for producing a CMOS circuit, operated as a lateral bipolar transistor MOS transistor with high current gain, based on the triple-well CMOS technology.

Als laterale Bipolartransistoren betriebene MOS-Transistoren sind bekannt: E. A. Vittoz, ”MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology”, IEEE Jornal of Solid-State Circuits, vol. sc-18, No. 3, pp 273–279, 1983 .As lateral bipolar transistors operated MOS transistors are known: EA Vittoz, "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology", IEEE Jornal of Solid-State Circuits, vol. sc-18, no. 3, pp 273-279, 1983 ,

Laterale NPN- und PNP-Transistoren mit hoher Stronverstärkung zur Herstellung von BiCMOS-Schaltkreisen mittels der CMOS-Technologie sind in der Patentliteratur beschrieben: US 6249031 und US 5326710 .High-gain lateral NPN and PNP transistors for producing BiCMOS circuits using CMOS technology are described in the patent literature: US 6249031 and US 5,327,710 ,

Ein spezieller Aufbau eines Bipolartransistors basierend auf der CMOS-Technologie (Triple-Well CMOS Technologie) wird beschrieben bei Zhiming Feng et al., ”Gate Controlled Vertical-Lateral NPN Bipolar Transistor in 90 nm RF CMOS Process”, Bipolar/BiCMOS Circuits uns Technology Meeting (BCTM), 2008 IEEE, Oct. 2008 .A specific structure of a bipolar transistor based on the CMOS technology (triple-well CMOS technology) is described in Zhiming Feng et al., "Gate Controlled Vertical-Lateral NPN Bipolar Transistor in 90nm RF CMOS Process", Bipolar / BiCMOS Circuits & Technology Meeting (BCTM), 2008 IEEE, Oct. 2008 ,

Die Weiterentwicklung auf dem Gebiet der integrierten Schaltkreise führt zu immer höheren Anforderungen an die Leistungsfähigkeit bestimmter integrierter Bauelementetypen. Eine dieser Forderungen ist die nach höheren Stromverstärkungswerten von lateralen MOS-Bauelementen bei hoher Datenreproduzierbarkeit des einzelnen Bauelements als Bestandteil der integrierten Schaltung. Die aus den oben erwähnten Veröffentlichungen bekannten Herstellungsverfahren genügen den erhöhten Ansprüchen nicht.The advancement in the field of integrated circuits leads to ever higher demands on the performance of certain integrated device types. One of these requirements is the higher current gain values of lateral MOS devices with high data reproducibility of the single device as part of the integrated circuit. The known from the publications mentioned above manufacturing methods do not meet the increased claims.

Ausgehend von dem bekannten Stand der Technik liegt der Erfindung folgendes technische Problem zugrunde: Die Stromverstärkung eines als lateraler Bipolar-Transistor betriebenen MOS-Transistors mit hoher Stromverstärkung hängt vor allem von der lateralen Basisweite ab, die der Kanallänge entspricht. Dabei gilt prinzipiell: Je kleiner die Kanallänge (Basisweite) ist, desto größer wird die Stromverstärkung, aber auch deren Streueung. Zusätzlich verschlechtert sich auch die Datengleichheit (Matching) von Transistorpaaren, bei denen es auf Gleichheit ankommt, z. B. Differenzeingangsstufen von Operationsverstärkern.Based on the known prior art, the invention is based on the following technical problem: The current amplification of a current operated as a lateral bipolar transistor MOS transistor with high current gain depends mainly on the lateral base width, which corresponds to the channel length. In principle, the smaller the channel length (base width) is, the greater the current gain, but also its spread. In addition, the data matching of pairs of transistors, where equality is important, also deteriorates. B. differential input stages of operational amplifiers.

Idealerweise werden in analogen Präzisionsschaltungen alle positiven Eigenschaften gleichzeitig benötigt, d. h. hohe Stromverstärkung, geringe Streueung der Stromverstärkung und gutes Matching. Damit besteht ein grundsätzlicher Konflikt zwischen den Parametern Stromverstärkung und Matching.Ideally, in analog precision circuits, all positive characteristics are needed simultaneously, i. H. high current gain, low dispersion of current gain and good matching. There is thus a fundamental conflict between the parameters of current amplification and matching.

Ziel der Erfindung ist es, den erwähnten Konflikt zwischen der möglichst hohen Stromverstärkung und der Streuung der Stromverstärkungswerte zu entschärfen sowie die Genauigkeit der Stromverstärkungswerte einzelner integrierter als laterale Bipolartransistoren betriebener MOS-Transistoren zu erhöhen.The aim of the invention is to defuse the mentioned conflict between the highest possible current gain and the dispersion of the current amplification values as well as to increase the accuracy of the current amplification values of individual integrated MOS transistors operated as lateral bipolar transistors.

Der Erfindung liegt die Aufgabe zugrunde, eine Verfahrensweise nach dem Oberbegriff des Anspruchs 1 so zu gestalten, dass in einem CMOS-Schaltkreis integrierte, als laterale Bipolar-Transistoren betriebene MOS-Transistoren mit hoher Stromverstärkung und guten Matching-Eigenschaften mit verbesserter Ausbeute hergestellt werden können.The invention has for its object to make a method according to the preamble of claim 1 so that in a CMOS circuit integrated, operated as a lateral bipolar transistors MOS transistors with high current gain and good matching properties can be produced with improved yield ,

Gelöst wird diese Aufgabe mit den im Anspruch 1 angegebenen Merkmalen.This object is achieved with the features specified in claim 1.

Der Gegenstand des Anspruchs 1 weist die Vorteile auf, dass ein zusätzlicher Polysiliziumring, der nahe zum eigentlichen Polysilizium-Gate um den Kollektor des lateralen Bipolartransistors ausgebildet wird, der eine Ausbildung der Gatestrukturen bewirkt, die trotz sehr kleiner Kanallängen – und damit hoher Stromverstärkung – zu einer geringen Streuung der Stromverstärkungswerte und zu einer Verbesserung der Matching-Werte führt.The subject matter of claim 1 has the advantages that an additional polysilicon ring, which is formed near the actual polysilicon gate around the collector of the lateral bipolar transistor, which causes a formation of the gate structures, despite very small channel lengths - and thus high current gain - to a small dispersion of the current gain values and an improvement of the matching values.

Die Streuung der Stromverstärkung kann weiter reduziert werden, indem statt einem Emitterkontakt zwei Emitterkontakte verwendet werden.The dispersion of the current gain can be further reduced by using two emitter contacts instead of one emitter contact.

Die Erfindung wird nun beispielhaft anhand von für die Ausführung des Verfahrens angepassten Layout-Varianten unter Zuhilfenahme der Zeichnung erläutert.The invention will now be explained by way of example with reference to adapted for the execution of the method layout variants with the aid of the drawing.

Dabei soll bei Verwendung der Begriffe Ring, Ringgebiet und ringförmig ein auf das Zentrum bezogenes, dieses umlaufendes geschlossenes Gebietes bezeichnet werden, welches nicht an allen Punkten den gleichen Abstand vom Zentrum haben muss; wie z. B. ein viereckiges Ringgebiet.It should be referred to when using the terms ring, ring area and a ring on the center, this circumferential closed area, which does not have to have the same distance from the center at all points; such as B. a quadrangular ring area.

Es zeigen schematischIt show schematically

1 ein Layout zur Durchführung des erfindungsgemäßen Verfahrens für einen lateralen NPN-Bipolartransistor als Draufsicht mit einem Emitterkontakt, einer oktogonalen Ringstruktur von Emitter und Gate und quadratförmiger Struktur von Kollektor und zusätzlichem Polysiliziumring, 1 a layout for carrying out the method according to the invention for a lateral NPN bipolar transistor in plan view with an emitter contact, an octagonal ring structure of emitter and gate and square-shaped structure of collector and additional polysilicon ring,

2 ein Layout wie in 1, jedoch mit oktogonaler Struktur von Kollektor und zusätzlichem Polysiliziumring, 2 a layout like in 1 , but with octagonal structure of collector and additional polysilicon ring,

3 ein Layout wie in 1, jedoch mit gestreckter oktogonaler Ringstruktur von Emitter und Gate, mit zwei Emitterkontakten und rechteckförmiger Struktur von Kollektor und zusätzlichem Polysiliziumring, 3 a layout like in 1 , but with extended octagonal ring structure of emitter and gate, with two emitter contacts and rectangular structure of collector and additional polysilicon ring,

4 ein Layout wie 3, jedoch mit oktogonaler Struktur von Kollektor und zusätzlichem Polysiliziumring und 4 a layout like 3 , but with octagonal structure of collector and additional polysilicon ring and

5 den Querschnitt eines lateralen NPN-Bipolartransistors mit dem erfindungsgemäßen zusätzlichen Polysiliziumring, 5 the cross section of a lateral NPN bipolar transistor with the additional polysilicon ring according to the invention,

6 ein Layout zur Durchführung des erfindungsgemäßen Verfahrens für einen lateralen PNP-Bipolartransistor als Draufsicht mit einem Emitterkontakt, einer oktogonalen Ringstruktur von Emitter und Gate und quadratförmiger Struktur von Kollektor und zusätzlichem Polysiliziumring, 6 a layout for carrying out the method according to the invention for a lateral PNP bipolar transistor in plan view with an emitter contact, an octagonal ring structure of emitter and gate and square-shaped structure of collector and additional polysilicon ring,

7 ein Layout wie in 6 jedoch mit oktogonaler Struktur von Kollektor und zusätzlichem Polysiliziumring, 7 a layout like in 6 but with octagonal structure of collector and additional polysilicon ring,

8 ein Layout wie in 6, jedoch mit gestreckter oktogonaler Ringstruktur von Emitter und Gate, mit zwei Emitterkontakten und rechteckförmiger Struktur von Kollektor und zusätzlichem Polysiliziumring, 8th a layout like in 6 , but with extended octagonal ring structure of emitter and gate, with two emitter contacts and rectangular structure of collector and additional polysilicon ring,

9 ein Layout wie 8, jedoch mit oktogonaler Struktur von Kollektor und zusätzlichem Polysiliziumring und 9 a layout like 8th , but with octagonal structure of collector and additional polysilicon ring and

10 den Querschnitt eines lateralen PNP-Bipolartransistors mit dem erfindungsgemäßen zusätzlichen Polysiliziumring. 10 the cross section of a lateral PNP bipolar transistor with the additional polysilicon ring according to the invention.

1 zeigt das Layout mit dem das erfindungsgemäße Verfahren für die Herstellung eines lateralen NPN-Bipolartransistors ausgeführt werden kann. Dabei bildet der oktogonale Emitter (1) die zentrale Fläche, die vom inneren Kollektor (3) durch den oktogonalen Polysilizium-Gate-Ring (2) getrennt ist, unter dem sich das Basisgebiet befindet. Um den außen quadratischen Kollektor (3) befindet sich der zusätzliche Polysiliziumring (4), der mittels eines Polysiliziumsteges mit dem Polysilizium-Gate-Ring (2) verbunden ist. Um den zusätzlichen Polysiliziumring (4) herum wird die quadratförmige Basis (5) mittels Basiskontaktring (6) angeschlossen. Die Basis (5) wird quadratisch umschlossen von der tiefen N-Wanne (9), die den äußeren Kollektor bildet. Der äußere Kollektor (9) wird über einen N-Wannenring (8) und den äußeren Kollektoranschluss (7) ringförmig von der Oberfläche aus angeschlossen. 1 shows the layout with which the inventive method for the production of a lateral NPN bipolar transistor can be performed. The octagonal emitter ( 1 ) the central area of the inner collector ( 3 ) through the octagonal polysilicon gate ring ( 2 ), under which the base area is located. To the outside square collector ( 3 ) is the additional polysilicon ring ( 4 ) by means of a polysilicon land with the polysilicon gate ring ( 2 ) connected is. Around the additional polysilicon ring ( 4 ) around the square-shaped base ( 5 ) by means of a base contact ring ( 6 ) connected. The base ( 5 ) is enclosed square by the deep N-tub ( 9 ), which forms the outer collector. The outer collector ( 9 ) is connected via an N-tub ring ( 8th ) and the outer collector terminal ( 7 ) connected annularly from the surface.

2 zeigt ein weiteres Layout-Beispiel eines lateralen NPN-Transistors. Dabei bildet der oktogonale Emitter (1) das zentrale Gebiet, das vom inneren Kollektor (3) durch den oktogonalen Polysilizium-Gate-Ring (2) getrennt ist. Der oktogonale Kollektor (3) wird von dem zusätzlichen Polysilziumring (4) umschlossen, der mittels eines Polysiliziumstegs mit dem Polysilizium-Gate-Ring (2) verbunden ist. Um den Polysilizium-Ring (4) herum wird die rechteckförmige Basis (5) mittels des auf seiner Innenseite oktogonalen Basiskontaktrings (6) angeschlossen. Die Basis (5) wird rechteckig von der tiefen N-Wanne umschlossen, die den äußeren Kollektor bildet. Der äußere Kollektor wird über einen N-Wannen-Ring (8) und den äußeren Kollektoranschluss (7) ringförmig von der Oberfläche aus angeschlossen. 2 shows another layout example of a lateral NPN transistor. The octagonal emitter ( 1 ) the central area, that of the inner collector ( 3 ) through the octagonal polysilicon gate ring ( 2 ) is disconnected. The octagonal collector ( 3 ) is replaced by the additional polysilicon ring ( 4 ) surrounded by a polysilicon ridge with the polysilicon gate ring ( 2 ) connected is. To the polysilicon ring ( 4 ) around the rectangular base ( 5 ) by means of the octagonal base contact ring ( 6 ) connected. The base ( 5 ) is rectangularly enclosed by the deep N-tub, which forms the outer collector. The outer collector is connected via an N-well ring ( 8th ) and the outer collector terminal ( 7 ) connected annularly from the surface.

3 zeigt die gleiche Layoutstruktur wie 1 mit dem Unterschied, dass die Emitterfläche (1) so weit erweitert wurde, dass sie mit zwei Kontakten (10) angeschlossen werden kann. 3 shows the same layout structure as 1 with the difference that the emitter surface ( 1 ) has been extended to include two contacts ( 10 ) can be connected.

Sämtliche den Emitter (1) umgebende Strukturen sind entsprechend der Emittervergrößerung erweitert, so dass die Umschließungsmaße von 2 und 4 bestehen bleiben. 5 zeigt den Querschnitt durch einen lateralen NPN-Transistor mit dem zusätzlichen Polysiliziumring (4). Im Vergleich zu 1 bis 4 sind nur die Kontakte weggelassen. STI bezeichnet die Shallow Trench Isolation.All the emitter ( 1 ) surrounding structures are extended according to the emitter enlargement, so that the enclosure dimensions of 2 and 4 remain. 5 shows the cross section through a lateral NPN transistor with the additional polysilicon ring ( 4 ). Compared to 1 to 4 only the contacts are omitted. STI refers to the shallow trench isolation.

Das Layout für die lateralen PNP-Transistoren der 6 bis 9 ist bis zur Basis-Wanne (5) und deren Anschluss (6) prinzipiell gleich wie bei den äquivalenten Typen der lateralen NPN-Transistoren (1 bis 4); der Leitungstyp der verschiedenen Schichten ist jeweils umgekehrt. Die N-Basis (5) wird hier von einer zweiten N-Wanne (7) umschlossen, welche im P-Substrat liegt. FOX bezeichnet ein thermisches Oxid.The layout for the lateral PNP transistors of the 6 to 9 is up to the base tub ( 5 ) and their connection ( 6 ) in principle the same as in the equivalent types of the lateral NPN transistors ( 1 to 4 ); The conductivity type of the different layers is reversed. The N-base ( 5 ) is here by a second N-tub ( 7 ), which lies in the P-substrate. FOX denotes a thermal oxide.

10 zeigt den Querschnitt durch einen lateralen PNP-Transistor mit dem zusätzlichen Polysiliziumring (4). Im Vergleich zu 6 bis 9 sind nur die Kontakte weggelassen. 10 shows the cross section through a lateral PNP transistor with the additional polysilicon ring ( 4 ). Compared to 6 to 9 only the contacts are omitted.

BezugszeichenlisteLIST OF REFERENCE NUMBERS

Fig. 1 bis Fig. 4

1
Emitteranschluss (N+)
2
Polysilizium-Gate
3
Innerer Kollektoranschluss (N+)
4
zusätzlicher Polysiliziumring
5
Basis (P-Wanne)
6
Basisanschluss (P+)
7
äußerer Kollektoranschluss (N+)
8
äußerer Kollektor (N-Wanne)
9
Tiefe N-Wanne
10
Kontakt
Fig. 5
1
Emitteranschluss (N+)
2
Polysilizium-Gate
3
Innerer Kollektoranschluss (N+)
4
zusätzlicher Polysiliziumring
5
Basis (P-Wanne)
6
Basisanschluss (P+)
7
äußerer Kollektoranschluss (N+)
8
äußerer Kollektor (N-Wanne)
9
tiefe N-Wanne
Fig. 6 bis Fig. 9
1
Emitteranschluss (P+)
2
Polysilizium-Gate
3
Kollektoranschluss (P+)
4
Zusätzlicher Polysiliziumring
5
Basis (N-Wanne)
6
Basisanschluss (N+)
7
Tiefe N-Wanne
8
Kontakt
Fig. 10
1
Emitteranschluss (P+)
2
Polysilizium-Gate
3
Kollektoranschluss (P+)
4
zusätzlicher Polysiliziumring
5
Basis (N-Wanne)
6
Basisanschluss (N+)
7
tiefe N-Wanne
11
Substrat (P)
Fig. 1 to Fig. 4
1
Emitter terminal (N + )
2
Polysilicon gate
3
Inner collector connection (N +)
4
additional polysilicon ring
5
Base (P-tub)
6
Basic connection (P + )
7
outer collector connection (N + )
8th
outer collector (N-tub)
9
Deep N-tub
10
Contact
Fig. 5
1
Emitter terminal (N + )
2
Polysilicon gate
3
Inner collector connection (N + )
4
additional polysilicon ring
5
Base (P-tub)
6
Basic connection (P + )
7
outer collector connection (N + )
8th
outer collector (N-tub)
9
deep N-tub
FIG. 6 to FIG. 9
1
Emitter connection (P + )
2
Polysilicon gate
3
Collector connection (P + )
4
Additional polysilicon ring
5
Base (N-tub)
6
Basic connection (N + )
7
Deep N-tub
8th
Contact
Fig. 10
1
Emitter connection (P + )
2
Polysilicon gate
3
Collector connection (P + )
4
additional polysilicon ring
5
Base (N-tub)
6
Basic connection (N + )
7
deep N-tub
11
Substrate (P)

ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION

Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Zitierte PatentliteraturCited patent literature

  • US 6249031 [0003] US 6249031 [0003]
  • US 5326710 [0003] US 5326710 [0003]

Zitierte Nicht-PatentliteraturCited non-patent literature

  • E. A. Vittoz, ”MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology”, IEEE Jornal of Solid-State Circuits, vol. sc-18, No. 3, pp 273–279, 1983 [0002] EA Vittoz, "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology", IEEE Jornal of Solid-State Circuits, vol. sc-18, no. 3, pp 273-279, 1983 [0002]
  • Zhiming Feng et al., ”Gate Controlled Vertical-Lateral NPN Bipolar Transistor in 90 nm RF CMOS Process”, Bipolar/BiCMOS Circuits uns Technology Meeting (BCTM), 2008 IEEE, Oct. 2008 [0004] Zhiming Feng et al., "Gate Controlled Vertical-Lateral NPN Bipolar Transistor in 90nm RF CMOS Process", Bipolar / BiCMOS Circuits & Technology Meeting (BCTM), 2008 IEEE, Oct. 2008 [0004]

Claims (4)

Verfahren zur Verbesserung der Reproduzierbarkeit hoher Werte der Stromverstärkung von einem in einem CMOS-Schaltkreis integrierten, als lateraler Bipolar-Transistor betriebenen konzentrisch aufgebauten MOS-Transistor mit einem im Zentrum befindlichen Emitter (1) und Polysilizium-Gate (2), wobei ein zusätzlicher Polysiliziumring (4) mit möglichst gleichbleibendem Abstand zum Polysilizium-Gate (2) konzentrisch um den als Kollektoranschluss (3) des als Kollektor fungierenden Drain erzeugt wird, wobei der zusätzliche Polysiliziumring (4) mit dem Polysilizium-Gate (2) über einen Polysiliziumsteg verbunden wird und auf der Bauelementoberfläche verbleibt, und wobei dieser zusätzliche Polysiliziumring (4) einen Kantenabstand von der Kante des Polysilizium-Gate (2) vom Ein- bis Zweifachen der Breite des Polysilizium-Gate (2) hat und jeweils mit den selben Prozessschritten wie das Polysilizium-Gate (2) beim Polysilizium-Abscheiden und im photolithographischen Prozess beim Beschichten, Belichten und Ätzen erzeugt wird.Method for improving the reproducibility of high values of the current gain of a CMOS circuit, implemented as a lateral bipolar transistor concentrically constructed MOS transistor with a central emitter ( 1 ) and polysilicon gate ( 2 ), wherein an additional polysilicon ring ( 4 ) with as constant a distance as possible to the polysilicon gate ( 2 ) concentrically around the collector terminal ( 3 ) of the drain acting as a collector, wherein the additional polysilicon ring ( 4 ) with the polysilicon gate ( 2 ) is connected via a polysilicon web and remains on the device surface, and wherein this additional polysilicon ring ( 4 ) an edge distance from the edge of the polysilicon gate ( 2 ) from one to two times the width of the polysilicon gate ( 2 ) and in each case with the same process steps as the polysilicon gate ( 2 ) in polysilicon deposition and in the photolithographic process of coating, exposure and etching. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass der laterale Bipolartransistor ein NPN-Transistor ist und mittels der Triple-Well-CMOS-Technologie hergestellt wird.A method according to claim 1, characterized in that the lateral bipolar transistor is an NPN transistor and is manufactured by means of the triple-well CMOS technology. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass der laterale Bipolartransistor ein PNP-Transistoren ist und mittels Triple-Well-CMOS-Technologie hergestellt wird.A method according to claim 1, characterized in that the lateral bipolar transistor is a PNP transistors and is produced by triple-well CMOS technology. Verfahren nach den Ansprüchen 1 und 3, dadurch gekennzeichnet, dass die Stromverstärkung des parasitären vertikalen PNP-Transistors unterdrückt wird, indem eine tief diffundierte N-Wanne, welche die N-Basiswanne umschließt im P-Substart hergestellt wird.Method according to claims 1 and 3, characterized in that the current gain of the parasitic vertical PNP transistor is suppressed by making a deeply diffused N-type well enclosing the N-type base well in the P-type sub-type.
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