DE10340603A1 - Schaltungsanordnung zum Schutz vor elektrostatischer Entladung und Spannungsregeleinrichtung mit Schaltungsanordnung - Google Patents

Schaltungsanordnung zum Schutz vor elektrostatischer Entladung und Spannungsregeleinrichtung mit Schaltungsanordnung Download PDF

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Publication number
DE10340603A1
DE10340603A1 DE10340603A DE10340603A DE10340603A1 DE 10340603 A1 DE10340603 A1 DE 10340603A1 DE 10340603 A DE10340603 A DE 10340603A DE 10340603 A DE10340603 A DE 10340603A DE 10340603 A1 DE10340603 A1 DE 10340603A1
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DE
Germany
Prior art keywords
circuit device
voltage regulator
electrostatic discharge
discharge protection
controlled paths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10340603A
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English (en)
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DE10340603B4 (de
Inventor
Roman Riederer
Markus Muellauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10340603A priority Critical patent/DE10340603B4/de
Priority to TW093123734A priority patent/TWI242282B/zh
Priority to US10/931,170 priority patent/US7342760B2/en
Publication of DE10340603A1 publication Critical patent/DE10340603A1/de
Application granted granted Critical
Publication of DE10340603B4 publication Critical patent/DE10340603B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches

Abstract

Es ist eine Schaltungsanordnung zum Schutz gegen elektrostatische Entladung für einen Feldeffekttransistor (99) vorgesehen, die eine erste und eine zweite steuerbare Strecke (T1, T2) mit jeweils einem Steueranschluß (11, 21) aufweist, wobei die Steueranschlüsse der steuerbaren Strecken (T1, T2) mit einem Quellenanschluß (2) des Feldeffekttransistors (99) gekoppelt ist. Ein erster Anschluß (12) der ersten steuerbaren Strecke (T1) ist mit einem Steueranschluß (3) des Transistors (99) verbunden, und ein erster Anschluß (22) der zweiten steuerbaren Strecke (T2) ist mit einem Bulkanschluß (4) des unipolaren Transistors (99) verbunden. Zweite Anschlüsse (13, 23) der steuerbaren Strecken (T1, T2) sind mit dem Senkenanschluß (1) verbunden. Eine Spannungsregeleinrichtung weist die Schaltungsanordnung sowie einen Operationsverstärker (6) auf, der zur Erzeugung eines Steuersignals abhängig von einer Differenz zweier eingangsseitig angelegter Signale ausgebildet ist. Ein Steuerausgang des Operationsverstärkers (6) ist mit dem Steueranschluß (3) des Transistors (99) gekoppelt.
DE10340603A 2003-09-01 2003-09-01 Schaltungsanordnung und Spannungsregeleinrichtung mit Schaltungsanordnung Expired - Fee Related DE10340603B4 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10340603A DE10340603B4 (de) 2003-09-01 2003-09-01 Schaltungsanordnung und Spannungsregeleinrichtung mit Schaltungsanordnung
TW093123734A TWI242282B (en) 2003-09-01 2004-08-06 Circuit arrangement for protection against electrostatic discharge and voltage regulating device having a circuit arrangement
US10/931,170 US7342760B2 (en) 2003-09-01 2004-08-31 Circuit arrangement for protection against electrostatic discharge and voltage regulating device having a circuit arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10340603A DE10340603B4 (de) 2003-09-01 2003-09-01 Schaltungsanordnung und Spannungsregeleinrichtung mit Schaltungsanordnung

Publications (2)

Publication Number Publication Date
DE10340603A1 true DE10340603A1 (de) 2005-04-21
DE10340603B4 DE10340603B4 (de) 2009-06-10

Family

ID=34352754

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10340603A Expired - Fee Related DE10340603B4 (de) 2003-09-01 2003-09-01 Schaltungsanordnung und Spannungsregeleinrichtung mit Schaltungsanordnung

Country Status (3)

Country Link
US (1) US7342760B2 (de)
DE (1) DE10340603B4 (de)
TW (1) TWI242282B (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043490A1 (en) * 2004-09-02 2006-03-02 Texas Instruments Incorporated Electrostatic discharge (ESD) detection and protection
US9344078B1 (en) * 2015-01-22 2016-05-17 Infineon Technologies Ag Inverse current protection circuit sensed with vertical source follower

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19629511C2 (de) * 1996-03-16 1998-09-24 Winbond Electronics Corp Schutzschaltung gegen elektrostatische Entladungen
US5959332A (en) * 1994-08-19 1999-09-28 Stmicroelectronics, S.R.L. Electrostatic-discharge protection device and method for making the same
WO2001011685A1 (en) * 1999-08-06 2001-02-15 Sarnoff Corporation Double triggering mechanism for achieving faster turn-on
US20020130366A1 (en) * 2001-03-19 2002-09-19 Yasuyuki Morishita ESD protection circuit for a semiconductor integrated circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2101148T3 (es) * 1992-03-10 1997-07-01 Siemens Ag Circuito de proteccion para un mosfet de potencia, que acciona una carga inductiva.
DE4237489A1 (de) * 1992-11-06 1994-05-11 Bosch Gmbh Robert Schaltung zum Schutz eines MOSFET-Leistungstransistors
US5917689A (en) * 1996-09-12 1999-06-29 Analog Devices, Inc. General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuits
US6552879B2 (en) * 2001-01-23 2003-04-22 International Business Machines Corporation Variable voltage threshold ESD protection
US6678130B2 (en) * 2001-03-27 2004-01-13 Agilent Technologies, Inc. Voltage regulator with electrostatic discharge shunt
US7068482B2 (en) * 2003-03-14 2006-06-27 United Microelectronics Corp. BiCMOS electrostatic discharge power clamp

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959332A (en) * 1994-08-19 1999-09-28 Stmicroelectronics, S.R.L. Electrostatic-discharge protection device and method for making the same
DE19629511C2 (de) * 1996-03-16 1998-09-24 Winbond Electronics Corp Schutzschaltung gegen elektrostatische Entladungen
WO2001011685A1 (en) * 1999-08-06 2001-02-15 Sarnoff Corporation Double triggering mechanism for achieving faster turn-on
US20020130366A1 (en) * 2001-03-19 2002-09-19 Yasuyuki Morishita ESD protection circuit for a semiconductor integrated circuit

Also Published As

Publication number Publication date
DE10340603B4 (de) 2009-06-10
TWI242282B (en) 2005-10-21
US20050083622A1 (en) 2005-04-21
TW200511550A (en) 2005-03-16
US7342760B2 (en) 2008-03-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee