DE112004003153A5 - Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung - Google Patents

Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung Download PDF

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Publication number
DE112004003153A5
DE112004003153A5 DE112004003153.2T DE112004003153T DE112004003153A5 DE 112004003153 A5 DE112004003153 A5 DE 112004003153A5 DE 112004003153 T DE112004003153 T DE 112004003153T DE 112004003153 A5 DE112004003153 A5 DE 112004003153A5
Authority
DE
Germany
Prior art keywords
power consumption
reduced power
data transmission
transmission system
transmission circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE112004003153.2T
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English (en)
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DE112004003153B4 (de
Inventor
Dr.-Ing. Kiehl Oliver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Qimonda AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda AG filed Critical Qimonda AG
Publication of DE112004003153A5 publication Critical patent/DE112004003153A5/de
Application granted granted Critical
Publication of DE112004003153B4 publication Critical patent/DE112004003153B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4915—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using pattern inversion or substitution
DE112004003153.2T 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung Active DE112004003153B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/674,859 US7321628B2 (en) 2003-09-30 2003-09-30 Data transmission system with reduced power consumption
US10/674,859 2003-09-30

Publications (2)

Publication Number Publication Date
DE112004003153A5 true DE112004003153A5 (de) 2014-11-13
DE112004003153B4 DE112004003153B4 (de) 2016-01-07

Family

ID=34376966

Family Applications (3)

Application Number Title Priority Date Filing Date
DE112004003153.2T Active DE112004003153B4 (de) 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung
DE112004001830.7T Active DE112004001830B4 (de) 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung
DE112004003149.4T Active DE112004003149B4 (de) 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE112004001830.7T Active DE112004001830B4 (de) 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung
DE112004003149.4T Active DE112004003149B4 (de) 2003-09-30 2004-09-30 Datenübertragungssystem mit reduziertem Leistungsverbrauch, Verfahren und Übertragungsschaltung

Country Status (3)

Country Link
US (1) US7321628B2 (de)
DE (3) DE112004003153B4 (de)
WO (1) WO2005032086A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8069403B2 (en) * 2008-07-01 2011-11-29 Sandisk Technologies Inc. Majority voting logic circuit for dual bus width
JP2010212822A (ja) * 2009-03-09 2010-09-24 Toshiba Corp 通信システム、送信装置、及び受信装置
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US20150178193A1 (en) * 2012-07-11 2015-06-25 Industry-University Cooperation Foundation, Hanyang University Apparatus and method for managing flash memory by means of writing data pattern recognition

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1090112A (en) 1963-03-12 1967-11-08 Post Office Improvements in or relating to pulse transmission systems
US4667337A (en) 1985-08-28 1987-05-19 Westinghouse Electric Corp. Integrated circuit having outputs configured for reduced state changes
GB8912471D0 (en) 1989-05-31 1989-07-19 Int Computers Ltd Data transmission code
CA2044051A1 (en) 1990-06-29 1991-12-30 Paul C. Wade System and method for error detection and reducing simultaneous switching noise
US5572735A (en) * 1994-05-27 1996-11-05 Ast Research, Inc. Method and apparatus for discharging the output voltage of a DC power supply
US5572736A (en) 1995-03-31 1996-11-05 International Business Machines Corporation Method and apparatus for reducing bus noise and power consumption
US5825824A (en) 1995-10-05 1998-10-20 Silicon Image, Inc. DC-balanced and transition-controlled encoding method and apparatus
US6243779B1 (en) 1996-11-21 2001-06-05 Integrated Device Technology, Inc. Noise reduction system and method for reducing switching noise in an interface to a large width bus
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US5890005A (en) 1997-06-02 1999-03-30 Nokia Mobile Phones Limited Low power, low interconnect complexity microprocessor and memory interface
US6222389B1 (en) * 1999-03-25 2001-04-24 International Business Machines Corporation Assisted gunning transceiver logic (AGTL) bus driver
WO2001024466A1 (en) * 1999-09-29 2001-04-05 Silicon Graphics, Inc. Communication interface with terminated transmission lines
US6553445B1 (en) 2000-02-04 2003-04-22 Ati International Srl Method and apparatus for reducing noise associated with switched outputs
JP2002366419A (ja) * 2001-06-07 2002-12-20 Mitsubishi Electric Corp データ処理装置およびデータ処理方法
US7257163B2 (en) * 2001-09-12 2007-08-14 Silicon Image, Inc. Method and system for reducing inter-symbol interference effects in transmission over a serial link with mapping of each word in a cluster of received words to a single transmitted word
CN100431033C (zh) * 2002-06-20 2008-11-05 皇家飞利浦电子股份有限公司 使用信道代码编码和解码的方法和存储数据的设备
US6614287B1 (en) * 2002-08-13 2003-09-02 Sun Microsystems, Inc. Calibration technique for delay locked loop leakage current
US7113550B2 (en) * 2002-12-10 2006-09-26 Rambus Inc. Technique for improving the quality of digital signals in a multi-level signaling system

Also Published As

Publication number Publication date
US7321628B2 (en) 2008-01-22
DE112004003149B4 (de) 2014-11-06
US20050069043A1 (en) 2005-03-31
DE112004001830B4 (de) 2015-02-26
DE112004001830T5 (de) 2006-07-20
WO2005032086A1 (en) 2005-04-07
DE112004003153B4 (de) 2016-01-07

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