DE2861415D1 - Process for interconnecting two crossed conducting metal lines deposited on a substrate - Google Patents

Process for interconnecting two crossed conducting metal lines deposited on a substrate

Info

Publication number
DE2861415D1
DE2861415D1 DE7878101133T DE2861415T DE2861415D1 DE 2861415 D1 DE2861415 D1 DE 2861415D1 DE 7878101133 T DE7878101133 T DE 7878101133T DE 2861415 T DE2861415 T DE 2861415T DE 2861415 D1 DE2861415 D1 DE 2861415D1
Authority
DE
Germany
Prior art keywords
interconnecting
substrate
metal lines
conducting metal
lines deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7878101133T
Other languages
English (en)
Inventor
George Edward Alcorn
Raymond Weaver Hamaker
Geoffrey Brownell Stephens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2861415D1 publication Critical patent/DE2861415D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE7878101133T 1977-10-20 1978-10-13 Process for interconnecting two crossed conducting metal lines deposited on a substrate Expired DE2861415D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/843,901 US4172004A (en) 1977-10-20 1977-10-20 Method for forming dense dry etched multi-level metallurgy with non-overlapped vias

Publications (1)

Publication Number Publication Date
DE2861415D1 true DE2861415D1 (en) 1982-01-28

Family

ID=25291286

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7878101133T Expired DE2861415D1 (en) 1977-10-20 1978-10-13 Process for interconnecting two crossed conducting metal lines deposited on a substrate

Country Status (4)

Country Link
US (1) US4172004A (de)
EP (1) EP0002185B1 (de)
JP (1) JPS5462788A (de)
DE (1) DE2861415D1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
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US4229247A (en) * 1978-12-26 1980-10-21 International Business Machines Corporation Glow discharge etching process for chromium
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPS5595340A (en) * 1979-01-10 1980-07-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4381215A (en) * 1980-05-27 1983-04-26 Burroughs Corporation Method of fabricating a misaligned, composite electrical contact on a semiconductor substrate
JPS5710926A (en) * 1980-06-25 1982-01-20 Toshiba Corp Manufacture of semiconductor device
US4336295A (en) * 1980-12-22 1982-06-22 Eastman Kodak Company Method of fabricating a transparent metal oxide electrode structure on a solid-state electrooptical device
US4352716A (en) * 1980-12-24 1982-10-05 International Business Machines Corporation Dry etching of copper patterns
US4703392A (en) * 1982-07-06 1987-10-27 General Electric Company Microstrip line and method for fabrication
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
GB8316477D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
JPS60136337A (ja) * 1983-12-22 1985-07-19 モノリシツク・メモリ−ズ・インコ−ポレイテツド ２重層処理においてヒロツク抑制層を形成する方法及びその構造物
US4580332A (en) * 1984-03-26 1986-04-08 Advanced Micro Devices, Inc. Forming a conductive, protective layer for multilayer metallization
US4717449A (en) * 1984-04-25 1988-01-05 Honeywell Inc. Dielectric barrier material
US4713682A (en) * 1984-04-25 1987-12-15 Honeywell Inc. Dielectric barrier material
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
US4892845A (en) * 1984-08-31 1990-01-09 Texas Instruments Incorporated Method for forming contacts through a thick oxide layer on a semiconductive device
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
US4789760A (en) * 1985-04-30 1988-12-06 Advanced Micro Devices, Inc. Via in a planarized dielectric and process for producing same
JPS6276653A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体集積回路
US4840923A (en) * 1986-04-30 1989-06-20 International Business Machine Corporation Simultaneous multiple level interconnection process
US4786962A (en) * 1986-06-06 1988-11-22 Hewlett-Packard Company Process for fabricating multilevel metal integrated circuits and structures produced thereby
US5045150A (en) * 1986-09-11 1991-09-03 National Semiconductor Corp. Plasma etching using a bilayer mask
JPS63114214A (ja) * 1986-09-11 1988-05-19 フェアチャイルド　セミコンダクタ　コーポレーション 二層マスクを使用するプラズマエッチング
US5007984A (en) * 1987-09-28 1991-04-16 Mitsubishi Denki Kabushiki Kaisha Method for etching chromium film formed on substrate
GB2211348A (en) * 1987-10-16 1989-06-28 Philips Nv A method of forming an interconnection between conductive levels
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
EP0403571A4 (en) * 1988-03-31 1991-01-30 Advanced Micro Devices, Inc. Gate array structure and process to allow optioning at second metal mask only
US5084404A (en) * 1988-03-31 1992-01-28 Advanced Micro Devices Gate array structure and process to allow optioning at second metal mask only
US5023701A (en) * 1988-03-31 1991-06-11 Advanced Micro Devices, Inc. Gate array structure and process to allow optioning at second metal mask only
JP2947818B2 (ja) * 1988-07-27 1999-09-13 株式会社日立製作所 微細孔への金属穴埋め方法
JPH06160610A (ja) * 1989-12-26 1994-06-07 Xerox Corp 不連続多位相フレネルレンズ製造方法
US5627345A (en) * 1991-10-24 1997-05-06 Kawasaki Steel Corporation Multilevel interconnect structure
US5256597A (en) * 1992-09-04 1993-10-26 International Business Machines Corporation Self-aligned conducting etch stop for interconnect patterning
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
JPH07245343A (ja) * 1994-03-03 1995-09-19 Toshiba Corp 半導体装置及びその製造方法
TWI629007B (zh) 2012-12-21 2018-07-11 Philip Morris Products S. A. 包含氣流導向元件的煙品
US9761488B2 (en) * 2015-07-17 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for cleaning via of interconnect structure of semiconductor device structure
US9911488B2 (en) 2015-10-22 2018-03-06 Sandisk Technologies Llc Three dimensional non-volatile memory with shorting source line/bit line pairs
JP2018129481A (ja) * 2017-02-10 2018-08-16 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes
US3880684A (en) * 1973-08-03 1975-04-29 Mitsubishi Electric Corp Process for preparing semiconductor
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US3856648A (en) * 1973-12-19 1974-12-24 Texas Instruments Inc Method of forming contact and interconnect geometries for semiconductor devices and integrated circuits
US3969197A (en) * 1974-02-08 1976-07-13 Texas Instruments Incorporated Method for fabricating a thin film capacitor
US3951709A (en) * 1974-02-28 1976-04-20 Lfe Corporation Process and material for semiconductor photomask fabrication
US3930913A (en) * 1974-07-18 1976-01-06 Lfe Corporation Process for manufacturing integrated circuits and metallic mesh screens
FR2312114A1 (fr) * 1975-05-22 1976-12-17 Ibm Attaque de materiaux par ions reactifs
US3994793A (en) * 1975-05-22 1976-11-30 International Business Machines Corporation Reactive ion etching of aluminum
JPS51147286A (en) * 1975-06-13 1976-12-17 Nec Corp Manufacturing process of semiconductor
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers

Also Published As

Publication number Publication date
EP0002185A1 (de) 1979-06-13
EP0002185B1 (de) 1981-12-02
JPS5462788A (en) 1979-05-21
US4172004A (en) 1979-10-23

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee