DE2962989D1 - Multi-value fet read only memory - Google Patents

Multi-value fet read only memory

Info

Publication number
DE2962989D1
DE2962989D1 DE7979101716T DE2962989T DE2962989D1 DE 2962989 D1 DE2962989 D1 DE 2962989D1 DE 7979101716 T DE7979101716 T DE 7979101716T DE 2962989 T DE2962989 T DE 2962989T DE 2962989 D1 DE2962989 D1 DE 2962989D1
Authority
DE
Germany
Prior art keywords
memory
value fet
fet read
read
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979101716T
Other languages
English (en)
Inventor
Jr Kenneth E Beilstein
Harish N Kotecha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2962989D1 publication Critical patent/DE2962989D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
DE7979101716T 1978-06-13 1979-06-01 Multi-value fet read only memory Expired DE2962989D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/915,338 US4202044A (en) 1978-06-13 1978-06-13 Quaternary FET read only memory

Publications (1)

Publication Number Publication Date
DE2962989D1 true DE2962989D1 (en) 1982-07-22

Family

ID=25435589

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979101716T Expired DE2962989D1 (en) 1978-06-13 1979-06-01 Multi-value fet read only memory

Country Status (4)

Country Link
US (1) US4202044A (de)
EP (1) EP0006167B1 (de)
JP (1) JPS586239B2 (de)
DE (1) DE2962989D1 (de)

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US4192014A (en) * 1978-11-20 1980-03-04 Ncr Corporation ROM memory cell with 2n FET channel widths
JPS5580888A (en) * 1978-12-12 1980-06-18 Nippon Telegr & Teleph Corp <Ntt> Read only memory circuit
US4365172A (en) * 1980-01-11 1982-12-21 Texas Instruments Incorporated High current static MOS driver circuit with low DC power dissipation
US4327424A (en) * 1980-07-17 1982-04-27 International Business Machines Corporation Read-only storage using enhancement-mode, depletion-mode or omitted gate field-effect transistors
US4525810A (en) * 1980-07-28 1985-06-25 International Business Machines Corporation Semiconductor memory capable of both read/write and read-only operation
JPS5856199B2 (ja) * 1980-09-25 1983-12-13 株式会社東芝 半導体記憶装置
CA1167963A (en) * 1980-12-24 1984-05-22 Mostek Corporation Multi-bit read only memory cell sensing circuit
WO1982002276A1 (en) * 1980-12-24 1982-07-08 Jiang Ching Lin Multi-bit read only memory cell sensing circuit
US4404655A (en) * 1981-01-28 1983-09-13 General Instrument Corporation Data sense apparatus for use in multi-threshold read only memory
US4415992A (en) * 1981-02-25 1983-11-15 Motorola, Inc. Memory system having memory cells capable of storing more than two states
US4449203A (en) * 1981-02-25 1984-05-15 Motorola, Inc. Memory with reference voltage generator
JPS581199A (ja) * 1981-06-26 1983-01-06 株式会社リコー 音声合成用リ−ドオンリ−メモリ
JPS586681U (ja) * 1981-07-07 1983-01-17 ブリヂストンサイクル株式会社 自転車用フロントバツグ
US4462088A (en) * 1981-11-03 1984-07-24 International Business Machines Corporation Array design using a four state cell for double density
US4447746A (en) * 1981-12-31 1984-05-08 International Business Machines Corporation Digital photodetectors
JPS58137181A (ja) * 1982-02-05 1983-08-15 Toshiba Corp 半導体メモリ
EP0110958A4 (de) * 1982-06-04 1986-09-23 Haluk M Aytac Mos logische schaltung auf drei ebenen.
US4518875A (en) * 1982-06-04 1985-05-21 Aytac Haluk M Three-level MOS logic circuit
JPS5949022A (ja) * 1982-09-13 1984-03-21 Toshiba Corp 多値論理回路
US4604732A (en) * 1984-05-29 1986-08-05 Thomson Components-Mostek Corporation Power supply dependent voltage reference circuit
US4914614A (en) * 1986-03-04 1990-04-03 Omron Tateisi Electronics Co. Multivalued ALU
US4805142A (en) * 1986-07-01 1989-02-14 International Business Machines Corporation Multiple ROM data state, read/write memory cell
US5268319A (en) 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
US4999525A (en) * 1989-02-10 1991-03-12 Intel Corporation Exclusive-or cell for pattern matching employing floating gate devices
US4904881A (en) * 1989-02-10 1990-02-27 Intel Corporation EXCLUSIVE-OR cell for neural network and the like
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5440505A (en) * 1994-01-21 1995-08-08 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element
US5515317A (en) * 1994-06-02 1996-05-07 Intel Corporation Addressing modes for a dynamic single bit per cell to multiple bit per cell memory
DE69521705D1 (de) * 1994-06-02 2001-08-16 Intel Corp Abtastverfahren für einen flash-speicher mit mehrstufigen zellen
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells
US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
US5485422A (en) * 1994-06-02 1996-01-16 Intel Corporation Drain bias multiplexing for multiple bit flash cell
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system
DE69523304T2 (de) * 1994-06-02 2002-07-11 Intel Corp Dynamischer speicher mit einem bis mehreren bits pro zelle
JP2768321B2 (ja) * 1995-02-28 1998-06-25 日本電気株式会社 半導体記憶装置
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US5635862A (en) * 1995-12-29 1997-06-03 Intel Corporation High-speed block id encoder circuit using dynamic logic
US5742543A (en) * 1996-08-19 1998-04-21 Intel Corporation Flash memory device having a page mode of operation
US6191995B1 (en) * 1999-08-30 2001-02-20 Micron Technology, Inc. Sharing signal lines in a memory device
ES2601193B1 (es) * 2015-08-11 2017-11-22 Fº JAVIER PORRAS VILA Aplicación de un lenguaje cuaternario para ordenador

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623023A (en) * 1967-12-01 1971-11-23 Sperry Rand Corp Variable threshold transistor memory using pulse coincident writing
GB1537114A (en) * 1975-08-29 1978-12-29 Tokyo Shibaura Electric Co Memory apparatus
US4142176A (en) * 1976-09-27 1979-02-27 Mostek Corporation Series read only memory structure
US4130891A (en) * 1977-08-08 1978-12-19 General Electric Company Methods of gray scale recording and archival memory target produced thereby
JPS5847795B2 (ja) * 1978-06-02 1983-10-25 セイコーエプソン株式会社 半導体記憶装置

Also Published As

Publication number Publication date
EP0006167B1 (de) 1982-06-02
US4202044A (en) 1980-05-06
EP0006167A1 (de) 1980-01-09
JPS586239B2 (ja) 1983-02-03
JPS54162934A (en) 1979-12-25

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee