DE3279313D1 - Full adder and operation circuit including a plurality of full adders - Google Patents

Full adder and operation circuit including a plurality of full adders

Info

Publication number
DE3279313D1
DE3279313D1 DE8282108974T DE3279313T DE3279313D1 DE 3279313 D1 DE3279313 D1 DE 3279313D1 DE 8282108974 T DE8282108974 T DE 8282108974T DE 3279313 T DE3279313 T DE 3279313T DE 3279313 D1 DE3279313 D1 DE 3279313D1
Authority
DE
Germany
Prior art keywords
full
circuit including
operation circuit
adders
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282108974T
Other languages
English (en)
Inventor
Masahide Ohhashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3279313D1 publication Critical patent/DE3279313D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
DE8282108974T 1981-12-03 1982-09-28 Full adder and operation circuit including a plurality of full adders Expired DE3279313D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194768A JPS5896347A (ja) 1981-12-03 1981-12-03 全加算器

Publications (1)

Publication Number Publication Date
DE3279313D1 true DE3279313D1 (en) 1989-02-02

Family

ID=16329911

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282108974T Expired DE3279313D1 (en) 1981-12-03 1982-09-28 Full adder and operation circuit including a plurality of full adders

Country Status (4)

Country Link
US (1) US4592007A (de)
EP (1) EP0081052B1 (de)
JP (1) JPS5896347A (de)
DE (1) DE3279313D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134932A (ja) * 1983-12-24 1985-07-18 Toshiba Corp プリチヤ−ジ型の桁上げ連鎖加算回路
US4709346A (en) * 1985-04-01 1987-11-24 Raytheon Company CMOS subtractor
EP0224656B1 (de) * 1985-09-30 1992-12-30 Siemens Aktiengesellschaft Mehrstelliger Carry-Ripple-Addierer in CMOS-Technik mit zwei Typen von Addiererzellen
DE3687778D1 (en) * 1985-09-30 1993-03-25 Siemens Ag Addierzelle fuer carry-ripple-addierer in cmos-technik.
JPH07104774B2 (ja) * 1985-11-26 1995-11-13 株式会社東芝 同期式演算回路
US5138959A (en) * 1988-09-15 1992-08-18 Prabhakar Kulkarni Method for treatment of hazardous waste in absence of oxygen
FR2716759B1 (fr) * 1994-02-28 1996-04-05 Sgs Thomson Microelectronics Etage de formatage d'opérandes optimisé.
US5875124A (en) * 1995-02-22 1999-02-23 Texas Instruments Japan Ltd. Full adder circuit
US5719528A (en) * 1996-04-23 1998-02-17 Phonak Ag Hearing aid device
US6356112B1 (en) 2000-03-28 2002-03-12 Translogic Technology, Inc. Exclusive or/nor circuit
US7260595B2 (en) * 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
GB2401962B (en) * 2003-05-23 2005-05-18 Arithmatica Ltd A sum bit generation circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602705A (en) * 1970-03-25 1971-08-31 Westinghouse Electric Corp Binary full adder circuit
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
US3843876A (en) * 1973-09-20 1974-10-22 Motorola Inc Electronic digital adder having a high speed carry propagation line
US4054788A (en) * 1976-06-04 1977-10-18 Hewlett-Packard Company Modular binary half-adder
US4254471A (en) * 1978-04-25 1981-03-03 International Computers Limited Binary adder circuit
US4463439A (en) * 1982-05-17 1984-07-31 International Business Machines Corporation Sum and carry outputs with shared subfunctions

Also Published As

Publication number Publication date
EP0081052A3 (en) 1986-02-05
JPS5896347A (ja) 1983-06-08
EP0081052B1 (de) 1988-12-28
EP0081052A2 (de) 1983-06-15
US4592007A (en) 1986-05-27
JPS6224815B2 (de) 1987-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee