DE3279493D1 - Method for the production of a semiconductor device comprising dielectrically isolating regions - Google Patents

Method for the production of a semiconductor device comprising dielectrically isolating regions

Info

Publication number
DE3279493D1
DE3279493D1 DE8282107889T DE3279493T DE3279493D1 DE 3279493 D1 DE3279493 D1 DE 3279493D1 DE 8282107889 T DE8282107889 T DE 8282107889T DE 3279493 T DE3279493 T DE 3279493T DE 3279493 D1 DE3279493 D1 DE 3279493D1
Authority
DE
Germany
Prior art keywords
production
semiconductor device
isolating regions
dielectrically isolating
dielectrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282107889T
Other languages
English (en)
Inventor
Tetsuya Ogawa
Nobuo Toyokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3279493D1 publication Critical patent/DE3279493D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
DE8282107889T 1981-09-10 1982-08-27 Method for the production of a semiconductor device comprising dielectrically isolating regions Expired DE3279493D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142911A JPS5848936A (ja) 1981-09-10 1981-09-10 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3279493D1 true DE3279493D1 (en) 1989-04-06

Family

ID=15326478

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282107889T Expired DE3279493D1 (en) 1981-09-10 1982-08-27 Method for the production of a semiconductor device comprising dielectrically isolating regions

Country Status (5)

Country Link
US (1) US4506434A (de)
EP (1) EP0074541B1 (de)
JP (1) JPS5848936A (de)
DE (1) DE3279493D1 (de)
IE (1) IE53844B1 (de)

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US4954459A (en) * 1988-05-12 1990-09-04 Advanced Micro Devices, Inc. Method of planarization of topologies in integrated circuit structures
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JPH03125608A (ja) * 1989-10-11 1991-05-29 Sumitomo Rubber Ind Ltd スノータイヤ
IT1236728B (it) * 1989-10-24 1993-03-31 Sgs Thomson Microelectronics Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati
US5027187A (en) * 1990-03-22 1991-06-25 Harris Corporation Polycrystalline silicon ohmic contacts to group III-arsenide compound semiconductors
JP2822656B2 (ja) * 1990-10-17 1998-11-11 株式会社デンソー 半導体装置およびその製造方法
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
DE4219592C2 (de) * 1991-06-17 2001-12-06 Gold Star Electronics Verfahren zur Ausbildung eines Graben-Isolationsbereichs mittels einer Reaktionsschicht
US5177028A (en) * 1991-10-22 1993-01-05 Micron Technology, Inc. Trench isolation method having a double polysilicon gate formed on mesas
US5330883A (en) * 1992-06-29 1994-07-19 Lsi Logic Corporation Techniques for uniformizing photoresist thickness and critical dimension of underlying features
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JP3024409B2 (ja) * 1992-12-25 2000-03-21 日本電気株式会社 半導体装置の製造方法
US5532191A (en) * 1993-03-26 1996-07-02 Kawasaki Steel Corporation Method of chemical mechanical polishing planarization of an insulating film using an etching stop
US5292683A (en) * 1993-06-09 1994-03-08 Micron Semiconductor, Inc. Method of isolating semiconductor devices and arrays of memory integrated circuitry
US5356828A (en) * 1993-07-01 1994-10-18 Digital Equipment Corporation Method of forming micro-trench isolation regions in the fabrication of semiconductor devices
US5521422A (en) * 1994-12-02 1996-05-28 International Business Machines Corporation Corner protected shallow trench isolation device
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
US6919260B1 (en) 1995-11-21 2005-07-19 Kabushiki Kaisha Toshiba Method of manufacturing a substrate having shallow trench isolation
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US5981354A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
JP3638778B2 (ja) 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
KR100382728B1 (ko) * 2000-12-09 2003-05-09 삼성전자주식회사 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법
DE10112638A1 (de) * 2001-03-16 2002-09-26 Harman Becker Automotive Sys Verfahren und Schaltungsanordnung zur Erzeugung des RDS-Bittaktes
US20050158963A1 (en) * 2004-01-20 2005-07-21 Advanced Micro Devices, Inc. Method of forming planarized shallow trench isolation
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
CN108593186B (zh) * 2018-06-20 2023-05-26 南京信息工程大学 一种基于双巨压阻传感器的井下压力探测装置及测量方法

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Also Published As

Publication number Publication date
IE822220L (en) 1983-03-10
EP0074541A3 (en) 1984-06-06
EP0074541B1 (de) 1989-03-01
IE53844B1 (en) 1989-03-15
JPS6229905B2 (de) 1987-06-29
JPS5848936A (ja) 1983-03-23
US4506434A (en) 1985-03-26
EP0074541A2 (de) 1983-03-23

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Legal Events

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8339 Ceased/non-payment of the annual fee