DE3315669A1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device contains a multiplicity of pixels arranged in matrix fashion. Each pixel contains an MOS field-effect transistor, and the field-effect transistors of the pixels are connected to rectangularly arranged row leads and column leads. The breakdown voltage of an insulating layer situated between a row lead and a column lead is greater than that of the gate insulating layer of the field-effect transistor.

Description

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description

The invention relates to a liquid crystal display device according to the preamble of patent claim 1. 5

Recently, large liquid crystal display devices have had picture elements in a matrix form are arranged, gained in importance and have been used in various devices such as small personal computers, small television receivers and the like. Investigated in particular for flat large display devices you can now use switching elements in the matrix arrangement.

Fig. 1 shows a matrix arrangement in which non-linear Elements in connection with liquid crystal picture elements are arranged in a matrix. The ones with non-linear Picture elements 2 equipped with elements are provided in the matrix within a display area 1.

Data or display signals and time control or

Addressing signals are fed to the picture elements 2 via column lines 3 and row lines 4, respectively. At the in The following errors can occur in the matrix arrangement shown in FIG. 1: Poor patterning of the column line, row wiring or non-linear elements, poor insulation at the intersection of column wiring 3 and row line 4, or poor insulation of the picture element 2. Of these errors can Bad patterns are excluded by improving the manufacturing process and careful keeping of the manufacturing facilities clean, thereby reducing the product yield increase. Improving the quality and increasing the thickness of an insulating layer would result in a decrease counteract the yield due to poor insulation at the beginning of the manufacturing process. To

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However, completing a matrix arrangement can be a poor insulation between lines due to static electricity or similar factors. When a column wire or a row wire is out of the display range of static electricity exposed, can be a bad one at an intersection between the perpendicularly crossing lines Isolation occur. The consequence of such poor insulation is that at the interface between the Row line and the column line data signals on the row line and addressing signals on the column line get what is called a line fault. The result would be that the display of all picture elements, connected to the poorly insulated line would be disturbed. This degrades the display of a Matrix arrangement noticeable. In general, when such a case occurs, the affected column line or the affected row line disconnected. However, this measure inevitably leads to a line fault that of the picture elements connected to the disconnected column line or to the disconnected row line come into a non-luminous or display-free state. If the matrix arrangement is on a single crystal Silicon substrate is formed, it can be made by a diode or a resistor in the silicon substrate static electricity. However, if the matrix arrangement comprises thin film transistors and is formed on a glass substrate, the aforementioned isolation strangles can easily occur because in this In case it is difficult to create a protection circuit against the ingress of static electricity. Hence results a poor production yield of the matrix arrangements due to poor insulation.

FIG. 2 is an equivalent circuit diagram of a picture element of FIG

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Matrix arrangement in which a MOS field effect transistor is used as a non-linear element. This transistor is denoted by 5 and is used to generate a data signal to a capacitor 6 and a control electrode 7-1 of a liquid crystal cell 7 to be applied. The condenser 6 is used to / hold a written data signal. The liquid crystal cell 7 contains the one already mentioned Control electrode 7-1, which is formed separately for each picture element / and a counter electrode 7-2 a top glass substrate.

FIG. 3a shows a top view of a detail of a picture element from FIG. 2, while FIG. 3b shows the cross-sectional view along the line AB in Fig. 3a. On a glass substrate 15 is a polycrystalline silicon layer 8 trained. By oxidizing the surface of the polycrystalline silicon layer 8, it is a gate insulating layer 13 formed. A second layer of polycrystalline silicon is formed thereon and through a Photo-etching process etched into a pattern / around the row line and the gate electrode 9 of a transistor at the same time as well as to create an electrode of the capacitor. Then a dopant is added to the second polycrystalline silicon layer 9 and 12 and into the first polycrystalline silicon layer 8 with the exception of that covered by the gate electrode 9 Area diffused to create the source and drain of the transistor. After that there is an insulating layer 14 are formed over the entire surface, and contact holes are formed in the region of the source region and the drain zone of the transistor introduced. Finally, a column line 10 and the control electrode are placed on this 11 of the picture element. The insulating layer 14 / the column line 10 from the row line 9 insulated, lies between electrodes 11 and 12, which form a capacitor. As the capacity of this

Capacitor of the thickness of the insulating 'is inversely proportional to ", the insulating layer 14 must be thin, so that a large capacitance of the capacitor is obtained. For example, if an image element has on all sides an edge length of 1 mm, the area may be of the capacitor only 200μ.ΐα ^2, so that the brightness of the display is not affected by the capacitor. If the insulating layer consisting of silicon oxide has a thickness of 0.5μπι, the capacitance of the capacitor is only about 2.5pF. On the other hand, the capacitance of the liquid crystal cell is in a picture element about 9pF if the thickness of the liquid crystal layer is 10μπι. The capacitance of the capacitor should be at least one, if possible two to three times that of a liquid crystal cell. To achieve this, the thickness of the insulating layer must be one fifth to one tenth of the above thickness or the area of the capacitor five to ten times as large as above be specified. However, since the area of the capacitor is limited to ensure the brightness of the display, reducing the thickness of the insulating layer between the capacitor electrodes is the only way to make the capacitance of the capacitor larger than that of the liquid crystal cell. So the silicon oxide layer should be 0.1μπι thick in this case. Even if silicon nitride, which has a larger dielectric constant, is used, the thickness of the insulating layer should be limited to 0.1 to 0.2 μm.

The gate insulating layer 13 of a transistor usually has a thickness of at least 0.1 to 0.2 μm. if the breakdown voltage of the transistor is to be high, the gate insulating layer must be 0.5μπι or more thick. Compared with the gate insulating layer 13, the breakdown voltage of the insulating layer 14 is half that

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high if both layers have the same thickness. This is because the gate insulating layer 13 is made of silicon oxide is thermally formed, while the insulating layer 14 made of silicon oxide by means of chemical vapor deposition is applied. When the thickness of the gate insulating layer

13 0.1 µm and that of the insulating layer 14 is 0.2μΐη,
then the breakdown voltage of the insulating layer 14 is
necessarily lower than that of the gate insulating layer 13. Static electricity in such a case would damage a row wiring or a

Column conduction inevitable at an intersection between the two be. With increasing thickness of the insulating layer

14 as protection against damage at the intersection between row lines and column line decreases the capacitance of the capacitor to a value less than that of one Liquid crystal cell is.

The object of the invention is to eliminate the problems identified and to create a liquid crystal display device in which, on the one hand, the capacitance of the capacitors is sufficiently large and, on the other hand, line faults due to the elimination of damage
static electricity can be avoided.

According to the invention, this object is achieved by the features
solved in claim 1.

Advantageous developments of the invention are in the
Characterized subclaims.

The invention is explained in more detail below on the basis of exemplary embodiments with reference to the drawings. Show it:

Fig. 1 shows a matrix arrangement of picture elements

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a liquid crystal display

direction,

2 shows an equivalent circuit diagram of a picture element;

Fig. 3a and

3b shows a detail of FIG. 2 in a plan view or a cross-sectional view,

Fig. 4a and

4b is a plan view and a cross-sectional view of an embodiment of the invention, respectively and

Fig. 5a and

5b shows a top view and a cross-sectional view of another embodiment the invention.

Fig. 4a shows a cross-sectional view corresponding to FIG. 3b of an embodiment of the invention in which a picture element is formed on a glass substrate 15. Figure 4b is a top view showing the interface between a row line 9 and a column line 10 shows. The same elements are provided with the same reference numbers as in FIG. 3. In addition to training the insulating layer 14 of FIG. 3 is present Drop a second silicon oxide layer on top of the whole Surface formed. The second silicon oxide layer is made using a photo-etching technique except in the area of Interface between row line 9 and column line 10 removed, as indicated by 14-2. Contact holes are then made in the region of the source zone and drain zone in the first silicon oxide layer 14-1 brought in. Finally, the column line 10 is

educated. The thickness of the first silicon oxide layer is 0.1 μΐη or less, so that the capacitor has a sufficient capacity. On the other hand the thickness of the second silicon oxide layer is 0.5μπι or more so that the breakdown voltage at the interface (overlap area) between the row wiring and the Column line is raised. With this structure according to the invention there is the advantage that the breakdown voltage at the interface between row line and column line can be higher than at the gate of the transistor and that the capacitance of the capacitor is sufficiently large. The second silicon oxide layer 14-2 can also are first formed and photo-etched before the first silicon oxide layer 14-1 is formed. if the first and second insulating layers are formed from the same material such as silicon oxide, the thicker insulating layer, which isolates row line 9 from column line 10, is much easier to photoetch than the thinner insulating layer. When the first insulating layer 14-1 is formed first and then the second insulating layer 14-2, it is more beneficial to have the two layers made of different materials form, for example, the first layer of silicon nitride and the second layer of silicon oxide, as alternately one of these layers is photo-etched for patterning.

Fig. 5 shows another embodiment of the invention. Fig. 5a is a plan view, Fig. 5b is a cross-sectional view along the chain line AB in Fig. 5a. Similar to Fig. 4, a thermal oxide layer 13 is formed on the surface of a silicon thin film 8, and second silicon thin films 9 and 12 are formed and patterned. In the second silicon thin films 9 and 12 and in the first silicon thin film 8 other than that of FIG

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Silicon layer 9 covered area becomes dopant doped. After forming the first insulating layer 14-1 and then the second insulating layer 14-2 the second insulating layer 14-2 is removed in the area of the capacitor electrode by a photo-etching technique, so that on the silicon film 12, which is one electrode of the capacitor represents, only the first insulating layer 14-1 remains. The following are contact holes in the area from the source zone and drain zone of a transistor into the

to insulating layer introduced. A column line 10 and a control electrode 11 for the picture element is finally formed. In this embodiment can through a thickness of about 0.1 μm of the first insulating layer 14-1 and a thickness of 0.5 µm or more of the second Insulating layer 14-2 the breakdown voltage at an interface between a column line and a Row line higher than that from the gate of the transistor. Furthermore, the capacitor of the picture element can be sufficient Have capacity. In addition, in the embodiment of FIG. 5, the transistorized picture element can pass such a thick insulating layer can be protected that the reliability is increased. As in Fig. 5a by a Indicated by dashed line 16, the thick insulating layer can essentially match the capacitor well or extend around it. The larger the recess in the insulating layer 14-2, the larger is the capacitance of the capacitor. The insulating layers 14-1 and 14-2 are usually made of silicon oxide. Besides but they can consist of silicon nitride or aluminum oxide. Similar to the embodiment of 4, the order of manufacture of the two insulating layers can be reversed.

Furthermore, the display area of the control electrode 11 can be enlarged by the fact that the control electrode is the

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Row line 9 and a part of the transistor covered. This can increase the brightness of the image. The coverage the row line 9 and part of the transistor with a control electrode 11 is particularly for the embodiment of Fig. 5 is suitable because the thick insulating layer 14-2 to avoid errors such as Short circuits.

As described above, according to the invention Breakdown voltage at the interface between a Column line and row line are made higher than that of the gate of a transistor by having an insulating layer in an area where column line and row line intersect is thicker than elsewhere.

Defects in a matrix arrangement due to static electricity can result in picture element defects to the exclusion of line defects be restricted. This improves the yield of the matrix arrangement, which enables mass production. In addition, the capacitance of the capacitor is so large that the matrix arrangement in terms of storage of data signals is improved. This leads to a better display with such a matrix arrangement equipped display device. In the embodiments described, the matrix arrangement comprises independent capacitor electrodes. However, the invention is also applicable to a matrix arrangement in which a capacitor electrode is formed from the row line of the adjacent picture element.

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Claims (4)

1.0 Claims 1 J Liquid crystal display device with a plurality of picture elements (2) arranged in a matrix, each of which is a liquid crystal cell (7) with a control electrode (7-1), a capacitor (6) for storing a data signal, and a MOS field effect transistor (5) for applying the data signal to the capacitor (6) and the control electrode (7-1), and a plurality of row lines (4, 9) and a plurality of column lines (3, 10) which are arranged at right angles to one another and connected to the Gate electrodes or the source electrodes of the MOS field effect transistors (5) of the picture elements (2) are connected, characterized in that the breakdown voltage of an insulating layer located between a column line (3, 10) and a row line (4, 9) is higher than the breakdown voltage of a Gate insulating layer (13) of the MOS field effect transistor (5). 2. Liquid crystal display device according to claim 1, characterized in that the thickness of the insulating layer (14-1, 14-2) at least at the interface between the row line (4, 9) and the column COPY line (3, 10) is larger than in other places. 3. Liquid crystal display device according to one of the preceding claims, characterized in that g e k e η η that at least part of the row line (4, 9) and / or the MOS field effect transistor (5) is covered by the control electrode (11) with the interposition of the insulating layer (14-1, 14-2). 4. Liquid crystal display device according to any one of preceding claims, characterized in that the picture elements (2) on one Glass substrate (15) are formed.