DE3379122D1 - Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion - Google Patents

Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion

Info

Publication number
DE3379122D1
DE3379122D1 DE8383304008T DE3379122T DE3379122D1 DE 3379122 D1 DE3379122 D1 DE 3379122D1 DE 8383304008 T DE8383304008 T DE 8383304008T DE 3379122 T DE3379122 T DE 3379122T DE 3379122 D1 DE3379122 D1 DE 3379122D1
Authority
DE
Germany
Prior art keywords
simultaneous
digital computer
instruction sets
multiple instruction
executing multiple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383304008T
Other languages
English (en)
Inventor
Howard Hunt Green
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE3379122D1 publication Critical patent/DE3379122D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
DE8383304008T 1982-07-14 1983-07-11 Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion Expired DE3379122D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/398,195 US4484272A (en) 1982-07-14 1982-07-14 Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion

Publications (1)

Publication Number Publication Date
DE3379122D1 true DE3379122D1 (en) 1989-03-09

Family

ID=23574376

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383304008T Expired DE3379122D1 (en) 1982-07-14 1983-07-11 Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion

Country Status (5)

Country Link
US (1) US4484272A (de)
EP (1) EP0099263B1 (de)
JP (1) JPS5998255A (de)
CA (1) CA1193740A (de)
DE (1) DE3379122D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862351A (en) * 1983-09-01 1989-08-29 Unisys Corporation Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same
US4811243A (en) * 1984-04-06 1989-03-07 Racine Marsh V Computer aided coordinate digitizing system
US5142681A (en) * 1986-07-07 1992-08-25 International Business Machines Corporation APL-to-Fortran translators
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
JP3053092B2 (ja) * 1987-06-05 2000-06-19 株式会社日立製作所 並列化コンパイル方法
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5347639A (en) * 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5408658A (en) * 1991-07-15 1995-04-18 International Business Machines Corporation Self-scheduling parallel computer system and method
US5867727A (en) * 1992-06-24 1999-02-02 Fujitsu Limited System for judging read out transfer word is correct by comparing flag of transfer word and lower bit portion of read destination selection address
US5699536A (en) * 1995-04-13 1997-12-16 International Business Machines Corporation Computer processing system employing dynamic instruction formatting
US5930490A (en) * 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US6842853B1 (en) * 1999-01-13 2005-01-11 Sun Microsystems, Inc. Thread suspension system and method
US20070005942A1 (en) * 2002-01-14 2007-01-04 Gil Vinitzky Converting a processor into a compatible virtual multithreaded processor (VMP)
WO2004049152A1 (en) * 2002-11-26 2004-06-10 Mplicity Ltd. A processor capable of multi-threaded execution of a plurality of instruction-sets
US7500210B2 (en) * 2006-11-15 2009-03-03 Mplicity Ltd. Chip area optimization for multithreaded designs
US20090044159A1 (en) * 2007-08-08 2009-02-12 Mplicity Ltd. False path handling
US8370820B2 (en) * 2009-10-20 2013-02-05 Guenthner Cynthia S Method and apparatus for enabling parallel processing during execution of a Cobol source program using two-stage compilation
US10318903B2 (en) 2016-05-06 2019-06-11 General Electric Company Constrained cash computing system to optimally schedule aircraft repair capacity with closed loop dynamic physical state and asset utilization attainment control

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623022A (en) * 1969-12-29 1971-11-23 Ibm Multiplexing system for interleaving operations of a processing unit
CA991751A (en) * 1971-07-30 1976-06-22 Western Electric Company, Incorporated Parallel element processing ensembles
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
JPS5390840A (en) * 1977-01-21 1978-08-10 Mitsubishi Electric Corp Arithmetic processor of microprogram control
JPS55159264A (en) * 1979-05-28 1980-12-11 Mitsubishi Electric Corp Computer processing system
US4346438A (en) * 1979-10-24 1982-08-24 Burroughs Corporation Digital computer having programmable structure
JPS56168272A (en) * 1980-05-29 1981-12-24 Fujitsu Ltd Parallel processing system for program of information processor
US4430708A (en) * 1981-05-22 1984-02-07 Burroughs Corporation Digital computer for executing instructions in three time-multiplexed portions

Also Published As

Publication number Publication date
JPS5998255A (ja) 1984-06-06
US4484272A (en) 1984-11-20
EP0099263A2 (de) 1984-01-25
EP0099263B1 (de) 1989-02-01
JPH0441378B2 (de) 1992-07-08
EP0099263A3 (en) 1986-11-26
CA1193740A (en) 1985-09-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee