DE3380603D1 - Method of logic simulation and logic simulation machine - Google Patents

Method of logic simulation and logic simulation machine

Info

Publication number
DE3380603D1
DE3380603D1 DE8383103164T DE3380603T DE3380603D1 DE 3380603 D1 DE3380603 D1 DE 3380603D1 DE 8383103164 T DE8383103164 T DE 8383103164T DE 3380603 T DE3380603 T DE 3380603T DE 3380603 D1 DE3380603 D1 DE 3380603D1
Authority
DE
Germany
Prior art keywords
logic simulation
machine
logic
simulation machine
simulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383103164T
Other languages
English (en)
Inventor
Metthew Christopher Graf
Robert Brewster Hitchcock
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3380603D1 publication Critical patent/DE3380603D1/de
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
DE8383103164T 1982-06-11 1983-03-30 Method of logic simulation and logic simulation machine Expired DE3380603D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/387,408 US4656580A (en) 1982-06-11 1982-06-11 Logic simulation machine

Publications (1)

Publication Number Publication Date
DE3380603D1 true DE3380603D1 (en) 1989-10-26

Family

ID=23529743

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383103164T Expired DE3380603D1 (en) 1982-06-11 1983-03-30 Method of logic simulation and logic simulation machine

Country Status (4)

Country Link
US (1) US4656580A (de)
EP (1) EP0096176B1 (de)
JP (1) JPS58222355A (de)
DE (1) DE3380603D1 (de)

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985002033A1 (en) * 1983-11-03 1985-05-09 Prime Computer, Inc. Digital system simulation method and apparatus
US4594677A (en) * 1983-11-09 1986-06-10 International Business Machines Corporation System for detecting and diagnosing noise caused by simultaneous current switching
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
JPS6165336A (ja) * 1984-09-07 1986-04-03 Hitachi Ltd 高速演算方式
JPS61102569A (ja) * 1984-10-26 1986-05-21 Hitachi Ltd 高速論理シミユレ−シヨン装置
JPS62182939A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 情報処理装置の論理シミユレ−シヨン方法
US4862347A (en) * 1986-04-22 1989-08-29 International Business Machine Corporation System for simulating memory arrays in a logic simulation machine
US4787061A (en) * 1986-06-25 1988-11-22 Ikos Systems, Inc. Dual delay mode pipelined logic simulator
US5126966A (en) * 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4787062A (en) * 1986-06-26 1988-11-22 Ikos Systems, Inc. Glitch detection by forcing the output of a simulated logic device to an undefined state
JPS63204441A (ja) * 1987-02-20 1988-08-24 Fujitsu Ltd 論理シミユレ−シヨン専用プロセツサの処理方式
US5093920A (en) * 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5572708A (en) * 1989-02-28 1996-11-05 Nec Corporation Hardware simulator capable of dealing with a description of a functional level
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5091872A (en) * 1989-06-23 1992-02-25 At&T Bell Laboratories Apparatus and method for performing spike analysis in a logic simulator
US5247650A (en) * 1989-08-30 1993-09-21 Industrial Technology Institute System for combining originally software incompatible control, kinematic, and discrete event simulation systems into a single integrated simulation system
KR0158887B1 (ko) * 1990-01-12 1999-02-18 이노우에 키요시 논리 모의실험기
US5327361A (en) * 1990-03-30 1994-07-05 International Business Machines Corporation Events trace gatherer for a logic simulation machine
JPH05205005A (ja) * 1990-03-30 1993-08-13 Internatl Business Mach Corp <Ibm> ロジック・シミュレーション・マシン用ホスト・インタフェース
US5247651A (en) * 1990-04-17 1993-09-21 At&T Bell Laboratories Interactive computer program specification and simulation system
US5237514A (en) * 1990-12-21 1993-08-17 International Business Machines Corporation Minimizing path delay in a machine by compensation of timing through selective placement and partitioning
US5500808A (en) * 1991-01-24 1996-03-19 Synopsys, Inc. Apparatus and method for estimating time delays using unmapped combinational logic networks
US5442772A (en) * 1991-03-29 1995-08-15 International Business Machines Corporation Common breakpoint in virtual time logic simulation for parallel processors
JP2680947B2 (ja) * 1991-09-12 1997-11-19 三菱電機株式会社 テストタイミングプログラム自動生成装置
EP0598149B1 (de) * 1992-11-12 2000-01-19 Fujitsu Limited Hardware Logiksimulator
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
JPH076142A (ja) * 1993-04-20 1995-01-10 Mitsubishi Electric Corp マルチエージェント協調システム及びその方法
JP3144950B2 (ja) * 1993-04-28 2001-03-12 富士通株式会社 論理シミュレーション方式
US5596505A (en) * 1993-07-23 1997-01-21 Vlsi Technology, Inc. Estimation of pin-to-pin timing for compiled blocks
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US6493658B1 (en) 1994-04-19 2002-12-10 Lsi Logic Corporation Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
US5963975A (en) * 1994-04-19 1999-10-05 Lsi Logic Corporation Single chip integrated circuit distributed shared memory (DSM) and communications nodes
US5875117A (en) * 1994-04-19 1999-02-23 Lsi Logic Corporation Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5815403A (en) * 1994-04-19 1998-09-29 Lsi Logic Corporation Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
US5557533A (en) * 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US5914887A (en) * 1994-04-19 1999-06-22 Lsi Logic Corporation Congestion based cost factor computing apparatus for integrated circuit physical design automation system
US6155725A (en) * 1994-04-19 2000-12-05 Lsi Logic Corporation Cell placement representation and transposition for integrated circuit physical design automation system
US5920712A (en) * 1994-05-13 1999-07-06 Quickturn Design Systems, Inc. Emulation system having multiple emulator clock cycles per emulated clock cycle
GB9413127D0 (en) * 1994-06-30 1994-08-24 Philips Electronics Uk Ltd Data processing apparatus
US5838908A (en) * 1994-11-14 1998-11-17 Texas Instruments Incorporated Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays
US5615127A (en) * 1994-11-30 1997-03-25 International Business Machines Corporation Parallel execution of a complex task partitioned into a plurality of entities
US5649164A (en) * 1994-12-30 1997-07-15 International Business Machines Corporation Sets and holds in virtual time logic simulation for parallel processors
US6058252A (en) * 1995-01-19 2000-05-02 Synopsys, Inc. System and method for generating effective layout constraints for a circuit design or the like
US5546562A (en) * 1995-02-28 1996-08-13 Patel; Chandresh Method and apparatus to emulate VLSI circuits within a logic simulator
US5632028A (en) * 1995-03-03 1997-05-20 Hal Computer Systems, Inc. Hardware support for fast software emulation of unimplemented instructions
US5819065A (en) * 1995-06-28 1998-10-06 Quickturn Design Systems, Inc. System and method for emulating memory
US5923865A (en) * 1995-06-28 1999-07-13 Quickturn Design Systems, Inc. Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US5868575A (en) * 1996-05-20 1999-02-09 Kuczewski; Robert M. Cooperative/interactive learning system for logic instruction
US5822564A (en) * 1996-06-03 1998-10-13 Quickturn Design Systems, Inc. Checkpointing in an emulation system
US5691910A (en) * 1996-06-10 1997-11-25 Lsi Logic Corporation Generic gate level model for characterization of glitch power in logic cells
US5872718A (en) * 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US5892688A (en) * 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US6030110A (en) * 1996-06-28 2000-02-29 Lsi Logic Corporation Advanced modular cell placement system with median control and increase in resolution
US5831863A (en) * 1996-06-28 1998-11-03 Lsi Logic Corporation Advanced modular cell placement system with wire length driven affinity system
US5870311A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US6085032A (en) * 1996-06-28 2000-07-04 Lsi Logic Corporation Advanced modular cell placement system with sinusoidal optimization
US5963455A (en) * 1996-06-28 1999-10-05 Lsi Logic Corporation Advanced modular cell placement system with functional sieve optimization technique
US6026223A (en) * 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US5870312A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with dispersion-driven levelizing system
US5914888A (en) * 1996-06-28 1999-06-22 Lsi Logic Corporation Advanced modular cell placement system with coarse overflow remover
US5812740A (en) * 1996-06-28 1998-09-22 Lsi Logic Corporation Advanced modular cell placement system with neighborhood system driven optimization
US5808899A (en) * 1996-06-28 1998-09-15 Lsi Logic Corporation Advanced modular cell placement system with cell placement crystallization
US5835381A (en) * 1996-06-28 1998-11-10 Lsi Logic Corporation Advanced modular cell placement system with minimizing maximal cut driven affinity system
US5867398A (en) * 1996-06-28 1999-02-02 Lsi Logic Corporation Advanced modular cell placement system with density driven capacity penalty system
US5844811A (en) * 1996-06-28 1998-12-01 Lsi Logic Corporation Advanced modular cell placement system with universal affinity driven discrete placement optimization
US5886904A (en) * 1996-09-23 1999-03-23 Quickturn Design Systems, Inc. Latch optimization in hardware logic emulation systems
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US6141636A (en) * 1997-03-31 2000-10-31 Quickturn Design Systems, Inc. Logic analysis subsystem in a time-sliced emulator
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6141631A (en) * 1998-03-25 2000-10-31 Lsi Logic Corporation Pulse rejection circuit model program and technique in VHDL
US6618698B1 (en) 1999-08-12 2003-09-09 Quickturn Design Systems, Inc. Clustered processors in an emulation engine
US6647349B1 (en) * 2000-03-31 2003-11-11 Intel Corporation Apparatus, method and system for counting logic events, determining logic event histograms and for identifying a logic event in a logic environment
US20020133325A1 (en) * 2001-02-09 2002-09-19 Hoare Raymond R. Discrete event simulator
US7260794B2 (en) * 2002-12-20 2007-08-21 Quickturn Design Systems, Inc. Logic multiprocessor for FPGA implementation
US7231336B2 (en) * 2003-08-25 2007-06-12 Legend Design Technology, Inc. Glitch and metastability checks using signal characteristics
US7684971B1 (en) * 2004-03-30 2010-03-23 Virtutech Ab Method and system for improving simulation performance
US7738398B2 (en) * 2004-06-01 2010-06-15 Quickturn Design Systems, Inc. System and method for configuring communication systems
US20070113219A1 (en) * 2005-11-17 2007-05-17 Microsoft Corporation Representing simulation values of variable in sharpley limited time and space
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
DE102008051401B4 (de) * 2008-10-11 2010-08-05 Festo Ag & Co. Kg Trainings- und Simulationsgerät für elektrische Funktionsabläufe in elektrischen, elektromechanischen und elektrofluidischen Anlagen
US8166431B1 (en) * 2009-08-20 2012-04-24 Xilinx, Inc. Reducing startup time of an embedded system that includes an integrated circuit
US8595683B1 (en) 2012-04-12 2013-11-26 Cadence Design Systems, Inc. Generating user clocks for a prototyping environment
RU2685980C1 (ru) * 2018-08-24 2019-04-23 Негосударственная автономная некоммерческая организация высшего образования "Институт мировых цивилизаций" Устройство для моделирования графика работы сотрудников учреждения

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3308285A (en) * 1963-04-19 1967-03-07 Rca Corp Logic networks for realizing associative logic functions
US3278732A (en) * 1963-10-29 1966-10-11 Ibm High speed multiplier circuit
GB1101851A (en) * 1965-01-20 1968-01-31 Ncr Co Generalized logic circuitry
US3381117A (en) * 1965-08-02 1968-04-30 Ibm Minimal pin multipurpose logic circuits
US3458240A (en) * 1965-12-28 1969-07-29 Sperry Rand Corp Function generator for producing the possible boolean functions of eta independent variables
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3614745A (en) * 1969-09-15 1971-10-19 Ibm Apparatus and method in a multiple operand stream computing system for identifying the specification of multitasks situations and controlling the execution thereof
DE2106257A1 (de) * 1971-02-10 1972-08-24 Philips Patentverwaltung Computer-Lehrspiel
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
US4087794A (en) * 1973-01-02 1978-05-02 International Business Machines Corporation Multi-level storage hierarchy emulation monitor
US3913070A (en) * 1973-02-20 1975-10-14 Memorex Corp Multi-processor data processing system
DE2321200C3 (de) * 1973-04-26 1984-01-26 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Durchführung logischer, durch Boolesche Gleichungen dargestellter Verknüpfungen
US3944985A (en) * 1973-10-19 1976-03-16 Texas Instruments Incorporated Workspace addressing system
FR2258113A5 (de) * 1973-11-30 1975-08-08 Honeywell Bull Soc Ind
GB1474385A (en) * 1973-12-14 1977-05-25 Int Computers Ltd Multiprocessor data processing systems
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
US4065808A (en) * 1975-01-25 1977-12-27 U.S. Philips Corporation Network computer system
JPS51117833A (en) * 1975-04-09 1976-10-16 Hitachi Ltd Group control system
US4015246A (en) * 1975-04-14 1977-03-29 The Charles Stark Draper Laboratory, Inc. Synchronous fault tolerant multi-processor system
SE7505552L (sv) * 1975-05-14 1976-11-15 Ellemtel Utvecklings Ab Sett och anordning att efter varandra avverka databehandlingsinstruktioner i funktionsenheter hos en datamaskin
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine

Also Published As

Publication number Publication date
EP0096176A3 (en) 1986-02-05
EP0096176A2 (de) 1983-12-21
JPS58222355A (ja) 1983-12-24
US4656580A (en) 1987-04-07
JPS633344B2 (de) 1988-01-22
EP0096176B1 (de) 1989-09-20

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee