DE3382234D1 - Verfahren und struktur zur verwendung beim konzept und aufbau elektronischer systeme in halbleitern. - Google Patents

Verfahren und struktur zur verwendung beim konzept und aufbau elektronischer systeme in halbleitern.

Info

Publication number
DE3382234D1
DE3382234D1 DE8383903852T DE3382234T DE3382234D1 DE 3382234 D1 DE3382234 D1 DE 3382234D1 DE 8383903852 T DE8383903852 T DE 8383903852T DE 3382234 T DE3382234 T DE 3382234T DE 3382234 D1 DE3382234 D1 DE 3382234D1
Authority
DE
Germany
Prior art keywords
semiconductors
concept
electronic systems
electronic
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383903852T
Other languages
English (en)
Inventor
Graham Shenton
G Jones
W Lucas
E Barton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Microelectronic Products
Original Assignee
International Microelectronic Products
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Microelectronic Products filed Critical International Microelectronic Products
Application granted granted Critical
Publication of DE3382234D1 publication Critical patent/DE3382234D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
DE8383903852T 1982-11-09 1983-11-03 Verfahren und struktur zur verwendung beim konzept und aufbau elektronischer systeme in halbleitern. Expired - Lifetime DE3382234D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/440,283 US4613940A (en) 1982-11-09 1982-11-09 Method and structure for use in designing and building electronic systems in integrated circuits
PCT/US1983/001704 WO1984002050A1 (en) 1982-11-09 1983-11-03 Method and structure for use in designing and building electronic systems in integrated circuits

Publications (1)

Publication Number Publication Date
DE3382234D1 true DE3382234D1 (de) 1991-05-02

Family

ID=23748165

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383903852T Expired - Lifetime DE3382234D1 (de) 1982-11-09 1983-11-03 Verfahren und struktur zur verwendung beim konzept und aufbau elektronischer systeme in halbleitern.

Country Status (4)

Country Link
US (1) US4613940A (de)
EP (1) EP0124598B1 (de)
DE (1) DE3382234D1 (de)
WO (1) WO1984002050A1 (de)

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JPH02189477A (ja) * 1989-01-19 1990-07-25 Mitsubishi Electric Corp 電子回路の測定仕様作成方法
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US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
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US5859781A (en) * 1994-09-13 1999-01-12 Lsi Logic Corporation Method and apparatus for computing minimum wirelength position (MWP) for cell in cell placement for integrated circuit chip
US5764534A (en) * 1994-10-13 1998-06-09 Xilinx, Inc. Method for providing placement information during design entry
US7068270B1 (en) * 1994-12-02 2006-06-27 Texas Instruments Incorporated Design of integrated circuit package using parametric solids modeller
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US5666288A (en) * 1995-04-21 1997-09-09 Motorola, Inc. Method and apparatus for designing an integrated circuit
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US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6584600B2 (en) 2001-02-15 2003-06-24 Hewlett-Packard Development Company, L.P. Hierarchical metal one usage tool for child level leaf cell
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US6871332B2 (en) * 2002-07-23 2005-03-22 Sun Microsystems, Inc. Structure and method for separating geometries in a design layout into multi-wide object classes
US7770144B2 (en) * 2003-05-28 2010-08-03 Eric Dellinger Modular array defined by standard cell logic
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US7345738B2 (en) * 2004-12-03 2008-03-18 Asml Netherlands B.V. Certified cells and method of using certified cells for fabricating a device
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US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
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US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
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Also Published As

Publication number Publication date
WO1984002050A1 (en) 1984-05-24
EP0124598A1 (de) 1984-11-14
US4613940A (en) 1986-09-23
EP0124598B1 (en) 1991-03-27
EP0124598A4 (de) 1987-06-11

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Legal Events

Date Code Title Description
8372 Publication of ep patent withdrawn