DE3382447D1 - Teilassoziativer sektorpufferspeicher. - Google Patents

Teilassoziativer sektorpufferspeicher.

Info

Publication number
DE3382447D1
DE3382447D1 DE8383103560T DE3382447T DE3382447D1 DE 3382447 D1 DE3382447 D1 DE 3382447D1 DE 8383103560 T DE8383103560 T DE 8383103560T DE 3382447 T DE3382447 T DE 3382447T DE 3382447 D1 DE3382447 D1 DE 3382447D1
Authority
DE
Germany
Prior art keywords
sub
sector buffer
associative
associative sector
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383103560T
Other languages
English (en)
Inventor
Howard T Olnowich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3382447D1 publication Critical patent/DE3382447D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
DE8383103560T 1982-05-26 1983-04-13 Teilassoziativer sektorpufferspeicher. Expired - Fee Related DE3382447D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/382,040 US4493026A (en) 1982-05-26 1982-05-26 Set associative sector cache

Publications (1)

Publication Number Publication Date
DE3382447D1 true DE3382447D1 (de) 1991-12-12

Family

ID=23507303

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383103560T Expired - Fee Related DE3382447D1 (de) 1982-05-26 1983-04-13 Teilassoziativer sektorpufferspeicher.

Country Status (4)

Country Link
US (1) US4493026A (de)
EP (1) EP0095033B1 (de)
JP (1) JPS58205975A (de)
DE (1) DE3382447D1 (de)

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US5291442A (en) * 1990-10-31 1994-03-01 International Business Machines Corporation Method and apparatus for dynamic cache line sectoring in multiprocessor systems
US5325504A (en) * 1991-08-30 1994-06-28 Compaq Computer Corporation Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system
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US5469555A (en) * 1991-12-19 1995-11-21 Opti, Inc. Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
US5345582A (en) * 1991-12-20 1994-09-06 Unisys Corporation Failure detection for instruction processor associative cache memories
US5537572A (en) * 1992-03-31 1996-07-16 Vlsi Technology, Inc. Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM)
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US5682515A (en) * 1993-01-25 1997-10-28 Benchmarq Microelectronics, Inc. Low power set associative cache memory with status inhibit of cache data output
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US5732243A (en) * 1994-10-18 1998-03-24 Cyrix Corporation Branch processing unit with target cache using low/high banking to support split prefetching
US5860149A (en) * 1995-06-07 1999-01-12 Emulex Corporation Memory buffer system using a single pointer to reference multiple associated data
US5845317A (en) * 1995-11-17 1998-12-01 Micron Technology, Inc. Multi-way cache expansion circuit architecture
US5809562A (en) * 1996-05-20 1998-09-15 Integrated Device Technology, Inc. Cache array select logic allowing cache array size to differ from physical page size
US6636944B1 (en) * 1997-04-24 2003-10-21 International Business Machines Corporation Associative cache and method for replacing data entries having an IO state
US6098152A (en) * 1997-10-17 2000-08-01 International Business Machines Corporation Method and apparatus for miss sequence cache block replacement utilizing a most recently used state
JPH11296263A (ja) * 1998-04-13 1999-10-29 Fujitsu Ltd プロセッサの初期設定制御装置
US6559851B1 (en) 1998-05-21 2003-05-06 Mitsubishi Electric & Electronics Usa, Inc. Methods for semiconductor systems for graphics processing
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US6535218B1 (en) 1998-05-21 2003-03-18 Mitsubishi Electric & Electronics Usa, Inc. Frame buffer memory for graphic processing
US6504550B1 (en) 1998-05-21 2003-01-07 Mitsubishi Electric & Electronics Usa, Inc. System for graphics processing employing semiconductor device
US6339813B1 (en) * 2000-01-07 2002-01-15 International Business Machines Corporation Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory
US6823434B1 (en) * 2000-02-21 2004-11-23 Hewlett-Packard Development Company, L.P. System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state
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KR100335500B1 (ko) * 2000-05-16 2002-05-08 윤종용 직접사상 캐쉬와 완전연관 버퍼를 포함한 캐쉬 시스템의제어 방법
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US7240277B2 (en) * 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
US7526610B1 (en) * 2008-03-20 2009-04-28 International Business Machines Corporation Sectored cache memory
US8464001B1 (en) * 2008-12-09 2013-06-11 Nvidia Corporation Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism
US8745334B2 (en) * 2009-06-17 2014-06-03 International Business Machines Corporation Sectored cache replacement algorithm for reducing memory writebacks
US9514055B2 (en) * 2009-12-31 2016-12-06 Seagate Technology Llc Distributed media cache for data storage systems
CN102859504B (zh) * 2010-04-21 2015-11-25 英派尔科技开发有限公司 复制数据的方法和系统以及获得数据副本的方法
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Also Published As

Publication number Publication date
JPS624745B2 (de) 1987-01-31
EP0095033A2 (de) 1983-11-30
JPS58205975A (ja) 1983-12-01
US4493026A (en) 1985-01-08
EP0095033A3 (en) 1987-04-29
EP0095033B1 (de) 1991-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee