DE3475995D1 - Master slice ic device - Google Patents

Master slice ic device

Info

Publication number
DE3475995D1
DE3475995D1 DE8484401568T DE3475995T DE3475995D1 DE 3475995 D1 DE3475995 D1 DE 3475995D1 DE 8484401568 T DE8484401568 T DE 8484401568T DE 3475995 T DE3475995 T DE 3475995T DE 3475995 D1 DE3475995 D1 DE 3475995D1
Authority
DE
Germany
Prior art keywords
master slice
slice
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484401568T
Other languages
English (en)
Inventor
Tetsu Tanizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3475995D1 publication Critical patent/DE3475995D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
DE8484401568T 1983-07-29 1984-07-26 Master slice ic device Expired DE3475995D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58137698A JPS6035532A (ja) 1983-07-29 1983-07-29 マスタスライス集積回路装置

Publications (1)

Publication Number Publication Date
DE3475995D1 true DE3475995D1 (en) 1989-02-09

Family

ID=15204716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401568T Expired DE3475995D1 (en) 1983-07-29 1984-07-26 Master slice ic device

Country Status (5)

Country Link
US (1) US4682202A (de)
EP (1) EP0133131B1 (de)
JP (1) JPS6035532A (de)
KR (1) KR890002966B1 (de)
DE (1) DE3475995D1 (de)

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US5019889A (en) * 1988-06-29 1991-05-28 Hitachi, Ltd. Semiconductor integrated circuit device
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US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
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JP2632420B2 (ja) * 1989-02-23 1997-07-23 三菱電機株式会社 半導体集積回路
US5107147A (en) * 1989-05-15 1992-04-21 Texas Instruments Incorporated Base cell for semi-custom circuit with merged technology
US4978633A (en) * 1989-08-22 1990-12-18 Harris Corporation Hierarchical variable die size gate array architecture
FR2653952A1 (fr) * 1989-10-31 1991-05-03 Thomson Composants Microondes Circuit integre logique prediffuse comportant au moins un amplificateur.
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US5015600A (en) * 1990-01-25 1991-05-14 Northern Telecom Limited Method for making integrated circuits
DE4002780C2 (de) * 1990-01-31 1995-01-19 Fraunhofer Ges Forschung Basiszelle für eine kanallose Gate-Array-Anordnung
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
JP2953755B2 (ja) * 1990-07-16 1999-09-27 株式会社東芝 マスタスライス方式の半導体装置
JP2609746B2 (ja) * 1990-07-19 1997-05-14 株式会社東芝 半導体装置
JP2714996B2 (ja) * 1990-08-08 1998-02-16 三菱電機株式会社 半導体集積回路装置
JPH04103161A (ja) * 1990-08-22 1992-04-06 Toshiba Corp バイポーラトランジスタ・絶縁ゲート型トランジスタ混載半導体装置
JPH04200013A (ja) * 1990-11-29 1992-07-21 Hitachi Ltd 論理回路
US5313119A (en) * 1991-03-18 1994-05-17 Crosspoint Solutions, Inc. Field programmable gate array
US6675361B1 (en) 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
US5671397A (en) * 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US5391943A (en) * 1994-01-10 1995-02-21 Mahant-Shetti; Shivaling S. Gate array cell with predefined connection patterns
US5440153A (en) * 1994-04-01 1995-08-08 United Technologies Corporation Array architecture with enhanced routing for linear asics
US5629636A (en) * 1994-10-19 1997-05-13 Crosspoint Solutions, Inc. Ram-logic tile for field programmable gate arrays
US5465055A (en) * 1994-10-19 1995-11-07 Crosspoint Solutions, Inc. RAM-logic tile for field programmable gate arrays
JP3152145B2 (ja) * 1996-02-28 2001-04-03 日本電気株式会社 半導体装置
JP3768433B2 (ja) * 2001-11-19 2006-04-19 株式会社ルネサステクノロジ 半導体装置の設計方法
JP2005268245A (ja) * 2004-03-16 2005-09-29 Nec Electronics Corp 半導体装置の製造方法
US7604947B2 (en) * 2004-06-09 2009-10-20 Cornell Research Foundation, Inc. Detection and modulation of cancer stem cells
US7402846B2 (en) * 2005-10-20 2008-07-22 Atmel Corporation Electrostatic discharge (ESD) protection structure and a circuit using the same
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7943967B2 (en) * 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US7932545B2 (en) * 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
DK1945821T3 (da) 2006-06-06 2011-03-07 Gen Probe Inc Mærkede oligonukleotider og anvendelse deraf i fremgangsmåder til amplifikation af nukleinsyrer
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7888705B2 (en) * 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101749351B1 (ko) 2008-07-16 2017-06-20 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

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US3609479A (en) * 1968-02-29 1971-09-28 Westinghouse Electric Corp Semiconductor integrated circuit having mis and bipolar transistor elements
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS57181152A (en) * 1981-04-30 1982-11-08 Toshiba Corp Semiconductor integrated circuit device
JPS5856354A (ja) * 1981-09-30 1983-04-04 Hitachi Ltd マスタ−スライスｌｓｉ
JPS5871650A (ja) * 1981-10-26 1983-04-28 Hitachi Ltd 半導体集積回路装置
JPS5885558A (ja) * 1981-11-17 1983-05-21 Olympus Optical Co Ltd セミカスタム半導体装置
JPS5890758A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 相補形集積回路装置
GB2122417B (en) * 1982-06-01 1985-10-09 Standard Telephones Cables Ltd Integrated circuits
JPS59177944A (ja) * 1983-03-28 1984-10-08 Hitachi Ltd 半導体集積回路装置
JPH0669142B2 (ja) * 1983-04-15 1994-08-31 株式会社日立製作所 半導体集積回路装置

Also Published As

Publication number Publication date
KR890002966B1 (ko) 1989-08-14
EP0133131A2 (de) 1985-02-13
EP0133131B1 (de) 1989-01-04
EP0133131A3 (en) 1986-01-22
KR850000800A (ko) 1985-03-09
JPS6035532A (ja) 1985-02-23
US4682202A (en) 1987-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee