DE3484285D1 - Mehrchip-synchronisationsfehlererkennung und -korrektur. - Google Patents

Mehrchip-synchronisationsfehlererkennung und -korrektur.

Info

Publication number
DE3484285D1
DE3484285D1 DE8484103513T DE3484285T DE3484285D1 DE 3484285 D1 DE3484285 D1 DE 3484285D1 DE 8484103513 T DE8484103513 T DE 8484103513T DE 3484285 T DE3484285 T DE 3484285T DE 3484285 D1 DE3484285 D1 DE 3484285D1
Authority
DE
Germany
Prior art keywords
correction
error detection
synchronization error
chip synchronization
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484103513T
Other languages
English (en)
Inventor
Price Ward Oman
Mark Anthony Rinaldi
Vito William Russo
Gregory Salyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3484285D1 publication Critical patent/DE3484285D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
DE8484103513T 1983-06-20 1984-03-30 Mehrchip-synchronisationsfehlererkennung und -korrektur. Expired - Fee Related DE3484285D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/506,488 US4635186A (en) 1983-06-20 1983-06-20 Detection and correction of multi-chip synchronization errors

Publications (1)

Publication Number Publication Date
DE3484285D1 true DE3484285D1 (de) 1991-04-25

Family

ID=24014809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484103513T Expired - Fee Related DE3484285D1 (de) 1983-06-20 1984-03-30 Mehrchip-synchronisationsfehlererkennung und -korrektur.

Country Status (4)

Country Link
US (1) US4635186A (de)
EP (1) EP0129006B1 (de)
JP (1) JPS608941A (de)
DE (1) DE3484285D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979108A (en) * 1985-12-20 1990-12-18 Ag Communication Systems Corporation Task synchronization arrangement and method for remote duplex processors
JPS63240632A (ja) * 1987-03-27 1988-10-06 Nec Corp 情報処理装置
AU4212089A (en) * 1988-09-01 1990-04-02 Ronald L. YIN An improved modular processor, a computer incorporating same, and a method of operating same
US6247144B1 (en) * 1991-01-31 2001-06-12 Compaq Computer Corporation Method and apparatus for comparing real time operation of object code compatible processors
US5371872A (en) * 1991-10-28 1994-12-06 International Business Machines Corporation Method and apparatus for controlling operation of a cache memory during an interrupt
US5434997A (en) * 1992-10-02 1995-07-18 Compaq Computer Corp. Method and apparatus for testing and debugging a tightly coupled mirrored processing system
DE4237259A1 (de) * 1992-11-04 1994-05-05 Siemens Ag Anordnung zur Datenübertragung mit einem parallelen Bussystem
TW295646B (de) * 1995-01-25 1997-01-11 Ibm
JP3282470B2 (ja) * 1995-11-08 2002-05-13 三菱電機株式会社 パソコンを用いた数値制御装置及びその制御方法
US6026471A (en) * 1996-11-19 2000-02-15 International Business Machines Corporation Anticipating cache memory loader and method
US6470462B1 (en) * 1999-02-25 2002-10-22 Telefonaktiebolaget Lm Ericsson (Publ) Simultaneous resynchronization by command for state machines in redundant systems
JP3810368B2 (ja) * 2001-01-18 2006-08-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 内部ｕｓｂハブを有するシステムで電力を管理する方法およびシステム
US7256628B2 (en) * 2003-01-29 2007-08-14 Sun Microsystems, Inc. Speed-matching control method and circuit
US10769329B1 (en) * 2019-04-03 2020-09-08 Synopsys, Inc. Retention model with RTL-compatible default operating mode
CN112763960B (zh) * 2021-01-04 2022-11-18 山东电工电气集团有限公司 一种就地模块的自运维方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE625673A (de) * 1961-12-04
US3462742A (en) * 1966-12-21 1969-08-19 Rca Corp Computer system adapted to be constructed of large integrated circuit arrays
GB1225253A (de) * 1967-09-12 1971-03-17
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
CH556576A (de) * 1973-03-28 1974-11-29 Hasler Ag Einrichtung zur synchronisierung dreier rechner.
US3970995A (en) * 1974-02-27 1976-07-20 Texas Instruments Incorporated Slaving calculator chips
JPS519352A (en) * 1974-07-11 1976-01-26 Hitachi Ltd Johoshorisochino koshokenshutsuhoshiki
GB1464570A (en) * 1974-11-27 1977-02-16 Ibm Microprogramme control units
JPS6038740B2 (ja) * 1976-04-19 1985-09-03 株式会社東芝 デ−タ処理装置
JPS5552170A (en) * 1978-10-09 1980-04-16 Toshiba Corp Composite computer system
US4309768A (en) * 1979-12-31 1982-01-05 Bell Telephone Laboratories, Incorporated Mismatch detection circuit for duplicated logic units
US4321666A (en) * 1980-02-05 1982-03-23 The Bendix Corporation Fault handler for a multiple computer system
JPS57130131A (en) * 1981-02-03 1982-08-12 Nippon Denso Co Ltd Multiple computer device

Also Published As

Publication number Publication date
EP0129006A2 (de) 1984-12-27
EP0129006A3 (en) 1988-01-20
JPS608941A (ja) 1985-01-17
EP0129006B1 (de) 1991-03-20
US4635186A (en) 1987-01-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee