DE3484328D1 - Datenverarbeitungssystem mit zwei prozessoren. - Google Patents

Datenverarbeitungssystem mit zwei prozessoren.

Info

Publication number
DE3484328D1
DE3484328D1 DE8484304903T DE3484328T DE3484328D1 DE 3484328 D1 DE3484328 D1 DE 3484328D1 DE 8484304903 T DE8484304903 T DE 8484304903T DE 3484328 T DE3484328 T DE 3484328T DE 3484328 D1 DE3484328 D1 DE 3484328D1
Authority
DE
Germany
Prior art keywords
processors
data processing
processing system
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484304903T
Other languages
English (en)
Inventor
Donald A Wade
Eric M Wagner
Lawrence W Krantz
R W Goodman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Application granted granted Critical
Publication of DE3484328D1 publication Critical patent/DE3484328D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port
DE8484304903T 1983-07-18 1984-07-18 Datenverarbeitungssystem mit zwei prozessoren. Expired - Fee Related DE3484328D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/515,089 US4591975A (en) 1983-07-18 1983-07-18 Data processing system having dual processors

Publications (1)

Publication Number Publication Date
DE3484328D1 true DE3484328D1 (de) 1991-05-02

Family

ID=24049933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484304903T Expired - Fee Related DE3484328D1 (de) 1983-07-18 1984-07-18 Datenverarbeitungssystem mit zwei prozessoren.

Country Status (7)

Country Link
US (1) US4591975A (de)
EP (1) EP0132157B1 (de)
JP (1) JPH0760427B2 (de)
KR (1) KR920004291B1 (de)
AU (1) AU580555B2 (de)
CA (1) CA1207915A (de)
DE (1) DE3484328D1 (de)

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US4722048A (en) * 1985-04-03 1988-01-26 Honeywell Bull Inc. Microcomputer system with independent operating systems
US5142625A (en) * 1985-06-12 1992-08-25 Minolta Camera Kabushiki Kaisha One-chip microcomputer including a programmable logic array for interrupt control
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US4920481A (en) * 1986-04-28 1990-04-24 Xerox Corporation Emulation with display update trapping
US5088033A (en) * 1986-04-28 1992-02-11 Xerox Corporation Data processing system emulation in a window with a coprocessor and I/O emulation
NL8602849A (nl) * 1986-11-11 1988-06-01 Philips Nv Inrichting voor het emuleren van een microcontroller, middels gebruik maken van een moedermicrocontroller en een dochtermicrocontroller, moedermicrocontroller, respektievelijk dochtermicrocontroller voor gebruik in zo een inrichting, geintegreerde schakeling voor gebruik in zo een dochtermicrocontroller en microcontroller bevattende zo een geintegreerde schakeling.
US5062040A (en) * 1986-12-22 1991-10-29 At&T Bell Laboratories Handling of notification of asynchronous events by user and stub processes of a distributed process executing on a plurality of processors of a multi-processor system
US5109329A (en) * 1987-02-06 1992-04-28 At&T Bell Laboratories Multiprocessing method and arrangement
US5003466A (en) * 1987-02-06 1991-03-26 At&T Bell Laboratories Multiprocessing method and arrangement
US5001624A (en) * 1987-02-13 1991-03-19 Harrell Hoffman Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
US4903218A (en) * 1987-08-13 1990-02-20 Digital Equipment Corporation Console emulation for a graphics workstation
US5091850A (en) * 1987-09-28 1992-02-25 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
US5157774A (en) * 1987-09-28 1992-10-20 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
US5870602A (en) * 1987-11-03 1999-02-09 Compaq Computer Corporation Multi-processor system with system wide reset and partial system reset capabilities
NZ226733A (en) * 1987-12-21 1990-05-28 Honeywell Bull Coupling incompatible cpu to data processing system
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
US5159686A (en) * 1988-02-29 1992-10-27 Convex Computer Corporation Multi-processor computer system having process-independent communication register addressing
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US5032982A (en) * 1988-05-18 1991-07-16 Zilog, Inc. Device for timing interrupt acknowledge cycles
US5124909A (en) * 1988-10-31 1992-06-23 Hewlett-Packard Company Software program for providing cooperative processing between personal computers and a host computer
US5283868A (en) * 1989-05-17 1994-02-01 International Business Machines Corp. Providing additional system characteristics to a data processing system through operations of an application program, transparently to the operating system
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5325517A (en) * 1989-05-17 1994-06-28 International Business Machines Corporation Fault tolerant data processing system
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
US5369749A (en) * 1989-05-17 1994-11-29 Ibm Corporation Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
US5144692A (en) * 1989-05-17 1992-09-01 International Business Machines Corporation System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system
US5369767A (en) * 1989-05-17 1994-11-29 International Business Machines Corp. Servicing interrupt requests in a data processing system without using the services of an operating system
US5113500A (en) * 1989-08-23 1992-05-12 Unisys Corporation Multiple cooperating and concurrently operating processors using individually dedicated memories
US5497497A (en) * 1989-11-03 1996-03-05 Compaq Computer Corp. Method and apparatus for resetting multiple processors using a common ROM
US6463529B1 (en) 1989-11-03 2002-10-08 Compaq Computer Corporation, Inc. Processor based system with system wide reset and partial system reset capabilities
US5167028A (en) * 1989-11-13 1992-11-24 Lucid Corporation System for controlling task operation of slave processor by switching access to shared memory banks by master processor
AU1971992A (en) * 1991-04-18 1992-11-17 Intel Corporation Method and apparatus for upgrading a computer processing system
US5761479A (en) * 1991-04-22 1998-06-02 Acer Incorporated Upgradeable/downgradeable central processing unit chip computer systems
EP0510241A3 (en) * 1991-04-22 1993-01-13 Acer Incorporated Upgradeable/downgradeable computer
US6446164B1 (en) * 1991-06-27 2002-09-03 Integrated Device Technology, Inc. Test mode accessing of an internal cache memory
EP0529142A1 (de) * 1991-08-30 1993-03-03 Acer Incorporated Ausbaubare und abbaubare Rechner
US5274834A (en) * 1991-08-30 1993-12-28 Intel Corporation Transparent system interrupts with integrated extended memory addressing
US5455912A (en) * 1993-06-18 1995-10-03 Vtech Industries, Inc. High speed/low overhead bus arbitration apparatus and method for arbitrating a system bus
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock
US5640592A (en) * 1994-09-30 1997-06-17 Mitsubishi Kasei America, Inc. System for transferring utility algorithm stored within a peripheral device to a host computer in a format compatible with the type of the host computer
US5815571A (en) * 1996-10-28 1998-09-29 Finley; Phillip Scott Computer system with secured data paths and method of protection
US6178493B1 (en) * 1998-02-19 2001-01-23 International Business Machines Corporation Multiprocessor stalled store detection
US7096358B2 (en) * 1998-05-07 2006-08-22 Maz Technologies, Inc. Encrypting file system
US6484309B2 (en) * 1998-10-08 2002-11-19 Intel Corporation Enabling software designed for one operating system to operate on another operating system
US6418505B1 (en) * 1998-12-17 2002-07-09 Ncr Corporation Accessing beyond memory address range of commodity operating system using enhanced operating system adjunct processor interfaced to appear as RAM disk
US9720861B2 (en) * 2014-12-02 2017-08-01 Qualcomm Incorporated Memory access by dual processor systems
US20180239912A1 (en) * 2017-02-22 2018-08-23 Ivo Icio Alexander Welch Data security method and local device with switch(es)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3242467A (en) * 1960-06-07 1966-03-22 Ibm Temporary storage register
US3715729A (en) * 1971-03-10 1973-02-06 Ibm Timing control for a multiprocessor system
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
US4123794A (en) * 1974-02-15 1978-10-31 Tokyo Shibaura Electric Co., Limited Multi-computer system
IT1055645B (it) * 1975-10-24 1982-01-11 Elsag Multielaboratore elettronico associativo per elabobazioni multiple contemporanee di dati in tempo reale
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
JPS5528102A (en) * 1978-08-15 1980-02-28 Toshiba Corp Composite computer system
US4402046A (en) * 1978-12-21 1983-08-30 Intel Corporation Interprocessor communication system
US4325116A (en) * 1979-08-21 1982-04-13 International Business Machines Corporation Parallel storage access by multiprocessors
FR2469752B1 (fr) * 1979-11-14 1986-05-16 Bull Sa Dispositif de partage d'un sous-systeme central d'un systeme de traitement de l'information en plusieurs sous-systemes independants
JPS5878250A (ja) * 1981-11-05 1983-05-11 Toshiba Corp マルチcpuマイコンシステム

Also Published As

Publication number Publication date
JPS60136856A (ja) 1985-07-20
AU2901484A (en) 1985-01-24
KR850001574A (ko) 1985-03-30
US4591975A (en) 1986-05-27
EP0132157A2 (de) 1985-01-23
CA1207915A (en) 1986-07-15
AU580555B2 (en) 1989-01-19
KR920004291B1 (ko) 1992-06-01
EP0132157A3 (en) 1987-11-25
JPH0760427B2 (ja) 1995-06-28
EP0132157B1 (de) 1991-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee