DE3583537D1 - Cmos-eingabe-/ausgabeschaltung. - Google Patents

Cmos-eingabe-/ausgabeschaltung.

Info

Publication number
DE3583537D1
DE3583537D1 DE8585106665T DE3583537T DE3583537D1 DE 3583537 D1 DE3583537 D1 DE 3583537D1 DE 8585106665 T DE8585106665 T DE 8585106665T DE 3583537 T DE3583537 T DE 3583537T DE 3583537 D1 DE3583537 D1 DE 3583537D1
Authority
DE
Germany
Prior art keywords
output switching
cmos input
cmos
input
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE8585106665T
Other languages
English (en)
Inventor
Hiroshi Yokouchi
Kazuhiko Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=14485697&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3583537(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE3583537D1 publication Critical patent/DE3583537D1/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/026—Shaping pulses by amplifying with a bidirectional operation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE8585106665T 1984-05-30 1985-05-30 Cmos-eingabe-/ausgabeschaltung. Revoked DE3583537D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59108475A JPS60252979A (ja) 1984-05-30 1984-05-30 Ｃｍｏｓ入出力回路

Publications (1)

Publication Number Publication Date
DE3583537D1 true DE3583537D1 (de) 1991-08-29

Family

ID=14485697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585106665T Revoked DE3583537D1 (de) 1984-05-30 1985-05-30 Cmos-eingabe-/ausgabeschaltung.

Country Status (5)

Country Link
US (1) US4680491A (de)
EP (1) EP0163305B1 (de)
JP (1) JPS60252979A (de)
KR (1) KR910001327B1 (de)
DE (1) DE3583537D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208251A (ja) * 1985-03-12 1986-09-16 Matsushita Electronics Corp 集積回路装置
JPS62197856A (ja) * 1986-02-25 1987-09-01 Matsushita Electric Ind Co Ltd マイクロコンピユ−タ
FR2609831B1 (fr) * 1987-01-16 1989-03-31 Thomson Semiconducteurs Circuit de lecture pour memoire
US4804864A (en) * 1987-03-09 1989-02-14 Rockwell International Corporation Multiphase CMOS toggle flip-flop
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
JPH01100656A (ja) * 1987-10-13 1989-04-18 Nec Corp マイクロコンピュータの出力回路
US4835418A (en) * 1987-11-17 1989-05-30 Xilinx, Inc. Three-state bidirectional buffer
US4908796A (en) * 1988-05-24 1990-03-13 Dallas Semiconductor Corporation Registered outputs for a memory device
US4987319A (en) * 1988-09-08 1991-01-22 Kawasaki Steel Corporation Programmable input/output circuit and programmable logic device
US4982115A (en) * 1989-02-02 1991-01-01 Rockwell International Corporation Digital signal direction detection circuit
JPH0821846B2 (ja) * 1989-02-03 1996-03-04 日本電気株式会社 ワイアード信号ドライブ回路
EP0420203A3 (en) * 1989-09-29 1991-06-19 Siemens Aktiengesellschaft Circuit for controlling a bidirectional bus drive
US5105105A (en) * 1990-03-21 1992-04-14 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
US5030853A (en) * 1990-03-21 1991-07-09 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
US5043606A (en) * 1990-03-30 1991-08-27 Seagate Technology, Inc. Apparatus and method for programmably controlling the polarity of an I/O signal of a magnetic disk drive
JP2604276B2 (ja) * 1990-11-20 1997-04-30 三菱電機株式会社 半導体記憶装置
JPH05233840A (ja) * 1991-08-23 1993-09-10 Oki Electric Ind Co Ltd 半導体装置
EP0574177B2 (de) * 1992-06-12 2003-08-20 Texas Instruments Incorporated Verfahren und Gerät zur Änderung der Taktfrequenz eines Prozessors
US5602496A (en) * 1992-06-17 1997-02-11 Advanced Micro Devices, Inc. Input buffer circuit including an input level translator with sleep function
US5424589A (en) * 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
US5324996A (en) * 1993-02-16 1994-06-28 Ast Research, Inc. Floating fault tolerant input buffer circuit
US5373470A (en) * 1993-03-26 1994-12-13 United Memories, Inc. Method and circuit for configuring I/O devices
JP3406444B2 (ja) * 1995-01-10 2003-05-12 富士通株式会社 データ転送システムのバス制御装置
US5517135A (en) * 1995-07-26 1996-05-14 Xilinx, Inc. Bidirectional tristate buffer with default input
CA2192426C (en) * 1996-01-03 2000-08-01 Richard Ng Bidirectional voltage translator
FR2753586B1 (fr) * 1996-09-18 1998-11-20 Sgs Thomson Microelectronics Circuit tampon de sortie de signaux logiques
US6023174A (en) * 1997-07-11 2000-02-08 Vanguard International Semiconductor Corporation Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols
JPH11175502A (ja) * 1997-12-08 1999-07-02 Mitsubishi Electric Corp 半導体装置
DE19855372A1 (de) * 1998-12-01 2000-06-08 Bosch Gmbh Robert Vorrichtung zur bidirektionalen Signalübertragung
JP2000183719A (ja) * 1998-12-11 2000-06-30 Nec Corp 入力回路、出力回路及び入出力回路、並びに該入出力回路を備えた信号伝送システム
KR100465599B1 (ko) 2001-12-07 2005-01-13 주식회사 하이닉스반도체 데이타 출력 버퍼
US7230450B2 (en) * 2004-05-18 2007-06-12 Intel Corporation Programming semiconductor dies for pin map compatibility
US7577029B2 (en) * 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
US7795914B2 (en) * 2007-11-02 2010-09-14 International Business Machines Corporation Circuit design methodology to reduce leakage power
US10322309B2 (en) 2014-09-19 2019-06-18 Doree Feldman Weighted garment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063225A (en) * 1976-03-08 1977-12-13 Rca Corporation Memory cell and array
JPS6041364B2 (ja) * 1980-08-29 1985-09-17 富士通株式会社 出力バッファ回路
JPH11774A (ja) * 1997-06-10 1999-01-06 Ishikawajima Harima Heavy Ind Co Ltd レーザ・ウォータジェット複合切断方法及び装置

Also Published As

Publication number Publication date
JPH0142013B2 (de) 1989-09-08
KR910001327B1 (ko) 1991-03-04
EP0163305B1 (de) 1991-07-24
EP0163305A2 (de) 1985-12-04
JPS60252979A (ja) 1985-12-13
EP0163305A3 (en) 1988-05-18
KR850008017A (ko) 1985-12-11
US4680491A (en) 1987-07-14

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8331 Complete revocation