DE3586177D1 - Datenstromsynchronisiereinrichtungen. - Google Patents

Datenstromsynchronisiereinrichtungen.

Info

Publication number
DE3586177D1
DE3586177D1 DE8585309200T DE3586177T DE3586177D1 DE 3586177 D1 DE3586177 D1 DE 3586177D1 DE 8585309200 T DE8585309200 T DE 8585309200T DE 3586177 T DE3586177 T DE 3586177T DE 3586177 D1 DE3586177 D1 DE 3586177D1
Authority
DE
Germany
Prior art keywords
data stream
synchronizers
data flow
elastic buffer
synchronizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585309200T
Other languages
English (en)
Other versions
DE3586177T2 (de
Inventor
Gerald L Bemis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3586177D1 publication Critical patent/DE3586177D1/de
Publication of DE3586177T2 publication Critical patent/DE3586177T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations
DE8585309200T 1984-12-18 1985-12-17 Datenstromsynchronisiereinrichtungen. Expired - Lifetime DE3586177T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/683,434 US4692894A (en) 1984-12-18 1984-12-18 Overflow/Underflow detection for elastic buffer

Publications (2)

Publication Number Publication Date
DE3586177D1 true DE3586177D1 (de) 1992-07-09
DE3586177T2 DE3586177T2 (de) 1992-12-03

Family

ID=24744027

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585309200T Expired - Lifetime DE3586177T2 (de) 1984-12-18 1985-12-17 Datenstromsynchronisiereinrichtungen.

Country Status (5)

Country Link
US (1) US4692894A (de)
EP (1) EP0188111B1 (de)
JP (1) JPS61146030A (de)
AT (1) ATE77025T1 (de)
DE (1) DE3586177T2 (de)

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KR102518285B1 (ko) 2021-04-05 2023-04-06 에스케이하이닉스 주식회사 PCIe 인터페이스 및 인터페이스 시스템
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Also Published As

Publication number Publication date
EP0188111A3 (en) 1988-10-05
DE3586177T2 (de) 1992-12-03
EP0188111A2 (de) 1986-07-23
JPS61146030A (ja) 1986-07-03
US4692894A (en) 1987-09-08
ATE77025T1 (de) 1992-06-15
EP0188111B1 (de) 1992-06-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee