DE3586551T2 - Integrierte halbleiterschaltung zum austausch von buszugriffberechtigungen zwischen mikroprozessoren. - Google Patents

Integrierte halbleiterschaltung zum austausch von buszugriffberechtigungen zwischen mikroprozessoren.

Info

Publication number: DE3586551T2
Authority: DE; Germany
Prior art keywords: microprocessors; access rights; semiconductor circuit; integrated semiconductor; bus access
Prior art date: 1984-05-31
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8585106559T

Other languages

English (en)

Other versions

DE3586551D1 (de

Inventor

Takumi Miyashita

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Ltd

Original Assignee

Fujitsu Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-05-31

Filing date

1985-05-29

Publication date

1993-02-11

1985-05-29 Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd

1992-10-01 Publication of DE3586551D1 publication Critical patent/DE3586551D1/de

1993-02-11 Application granted granted Critical

1993-02-11 Publication of DE3586551T2 publication Critical patent/DE3586551T2/de

2005-05-30 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

DE8585106559T 1984-05-31 1985-05-29 Integrierte halbleiterschaltung zum austausch von buszugriffberechtigungen zwischen mikroprozessoren. Expired - Fee Related DE3586551T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP59109477A JPH0690700B2 (ja)	1984-05-31	1984-05-31	半導体集積回路

Publications (2)

Publication Number	Publication Date
DE3586551D1 DE3586551D1 (de)	1992-10-01
DE3586551T2 true DE3586551T2 (de)	1993-02-11

Family

ID=14511228

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8585106559T Expired - Fee Related DE3586551T2 (de)	1984-05-31	1985-05-29	Integrierte halbleiterschaltung zum austausch von buszugriffberechtigungen zwischen mikroprozessoren.

Country Status (5)

Country	Link
US (1)	US4819158A (de)
EP (1)	EP0166248B1 (de)
JP (1)	JPH0690700B2 (de)
KR (1)	KR900007002B1 (de)
DE (1)	DE3586551T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5179678A (en) *	1987-09-08	1993-01-12	Nec Corporation	Address/control signal input circuit for a cache controller which clamps the address/control signals to predetermined logic level clamp signal is received
JPH0786870B2 (ja) *	1988-04-15	1995-09-20	株式会社日立製作所	コプロセツサのデータ転送制御方法およびその回路
US5440749A (en) *	1989-08-03	1995-08-08	Nanotronics Corporation	High performance, low cost microprocessor architecture
JP2762138B2 (ja) *	1989-11-06	1998-06-04	三菱電機株式会社	メモリコントロールユニット
US5119480A (en) *	1989-11-13	1992-06-02	International Business Machines Corporation	Bus master interface circuit with transparent preemption of a data transfer operation
JPH05324544A (ja)	1992-05-15	1993-12-07	Hitachi Ltd	バス制御方法
US5408612A (en) *	1992-09-09	1995-04-18	Digital Equipment Corporation	Microprocessor system for selectively accessing a processor internal register when the processor has control of the bus and partial address identifying the register
GB2326065B (en) *	1997-06-05	2002-05-29	Mentor Graphics Corp	A scalable processor independent on-chip bus
JP4030216B2 (ja) *	1999-03-09	2008-01-09	インターナショナル・ビジネス・マシーンズ・コーポレーション	マイクロプロセッサとマイクロプロセッサを含むシステム及びマイクロプロセッサのバスサイクル制御方法
US8956161B2 (en)	2008-11-04	2015-02-17	Duane C Keller	Article and method for controlling oral-originated systemic disease
US8905760B2 (en) *	2008-11-04	2014-12-09	Duane C. Keller	Methods and systems for progressively treating and controlling oral periopathogens causing systemic inflammations
US8591229B2 (en)	2010-12-16	2013-11-26	Duane C. Keller	Devices and methods for creating a positive pressure environment for treatment of oral biofilms associated with periodontal disease

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS5248440A (en) *	1975-10-15	1977-04-18	Toshiba Corp	Memory access control system
US4112490A (en) *	1976-11-24	1978-09-05	Intel Corporation	Data transfer control apparatus and method
US4275440A (en) *	1978-10-02	1981-06-23	International Business Machines Corporation	I/O Interrupt sequencing for real time and burst mode devices
US4240138A (en) *	1978-10-03	1980-12-16	Texas Instruments Incorporated	System for direct access to a memory associated with a microprocessor
US4348722A (en) *	1980-04-03	1982-09-07	Motorola, Inc.	Bus error recognition for microprogrammed data processor
JPS58169248A (ja) *	1982-03-30	1983-10-05	Fujitsu Ltd	入力条件セレクタ付プログラムカウンタ制御方式
US4488228A (en) *	1982-12-03	1984-12-11	Motorola, Inc.	Virtual memory data processor
US4602327A (en) *	1983-07-28	1986-07-22	Motorola, Inc.	Bus master capable of relinquishing bus on request and retrying bus cycle
US4720811A (en) *	1985-04-26	1988-01-19	Hitachi, Ltd.	Microprocessor capable of stopping its operation at any cycle time

1984
- 1984-05-31 JP JP59109477A patent/JPH0690700B2/ja not_active Expired - Lifetime
1985
- 1985-05-29 EP EP85106559A patent/EP0166248B1/de not_active Expired - Lifetime
- 1985-05-29 DE DE8585106559T patent/DE3586551T2/de not_active Expired - Fee Related
- 1985-05-30 US US06/739,338 patent/US4819158A/en not_active Expired - Lifetime
- 1985-05-31 KR KR1019850003804A patent/KR900007002B1/ko not_active IP Right Cessation

Also Published As

Publication number	Publication date
EP0166248B1 (de)	1992-08-26
US4819158A (en)	1989-04-04
JPS6111872A (ja)	1986-01-20
KR850008567A (ko)	1985-12-18
EP0166248A3 (en)	1988-09-14
DE3586551D1 (de)	1992-10-01
KR900007002B1 (ko)	1990-09-25
JPH0690700B2 (ja)	1994-11-14
EP0166248A2 (de)	1986-01-02

Legal Events

Date	Code	Title	Description
1993-09-23	8364	No opposition during term of opposition
1995-05-11	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE3579496D1 (de)	1990-10-11	Geraet zum transferieren von halbleiterplaettchen.
DE3171379D1 (en)	1985-08-22	Bus arrangement for interconnectiong circuit chips
DE3575635D1 (de)	1990-03-01	Kuehlungssystem fuer integrierte schaltungschips.
DE3582640D1 (de)	1991-05-29	Verzoegerungsschaltung fuer lsi-toranordnung.
KR910016235A (ko)	1991-09-30	반도체 집적회로
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
KR860005370A (ko)	1986-07-21	반도체 기억장치
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
KR860002824A (ko)	1986-04-30	반도체 기억장치
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3586551D1 (de)	1992-10-01	Integrierte halbleiterschaltung zum austausch von buszugriffberechtigungen zwischen mikroprozessoren.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
KR860005369A (ko)	1986-07-21	반도체 기억장치
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3586556T2 (de)	1993-01-14	Halbleiterspeicheranordnung.
DE3787357T2 (de)	1994-02-24	Steuerschaltung für Halbleiterspeicher.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE3786358D1 (de)	1993-08-05	Halbleiterspeicher mit system zum seriellen schnellzugriff.
DE3586675T2 (de)	1993-03-25	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.
DE3586810D1 (de)	1992-12-17	Halbleiterschaltung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3580454D1 (de)	1990-12-13	Halbleiterspeicheranordnung.