DE3668517D1 - Logischer schaltungsentwurf fuer hochintegrierte schaltkreise. - Google Patents

Logischer schaltungsentwurf fuer hochintegrierte schaltkreise.

Info

Publication number
DE3668517D1
DE3668517D1 DE8686112339T DE3668517T DE3668517D1 DE 3668517 D1 DE3668517 D1 DE 3668517D1 DE 8686112339 T DE8686112339 T DE 8686112339T DE 3668517 T DE3668517 T DE 3668517T DE 3668517 D1 DE3668517 D1 DE 3668517D1
Authority
DE
Germany
Prior art keywords
integrated circuits
circuit design
logical circuit
highly integrated
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686112339T
Other languages
English (en)
Inventor
Joseph Michael Fitzgerald
Pho Hoang Nguyen
Robert Russell Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3668517D1 publication Critical patent/DE3668517D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
DE8686112339T 1985-10-21 1986-09-05 Logischer schaltungsentwurf fuer hochintegrierte schaltkreise. Expired - Fee Related DE3668517D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/789,868 US4746966A (en) 1985-10-21 1985-10-21 Logic-circuit layout for large-scale integrated circuits

Publications (1)

Publication Number Publication Date
DE3668517D1 true DE3668517D1 (de) 1990-03-01

Family

ID=25148912

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686112339T Expired - Fee Related DE3668517D1 (de) 1985-10-21 1986-09-05 Logischer schaltungsentwurf fuer hochintegrierte schaltkreise.

Country Status (5)

Country Link
US (1) US4746966A (de)
EP (1) EP0219668B1 (de)
JP (1) JPS6298746A (de)
CA (1) CA1243424A (de)
DE (1) DE3668517D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2580301B2 (ja) * 1988-12-27 1997-02-12 株式会社日立製作所 半導体集積回路装置
US4978633A (en) * 1989-08-22 1990-12-18 Harris Corporation Hierarchical variable die size gate array architecture
JPH07111971B2 (ja) * 1989-10-11 1995-11-29 三菱電機株式会社 集積回路装置の製造方法
US5045913A (en) * 1990-01-29 1991-09-03 International Business Machines Corp. Bit stack compatible input/output circuits
US4988636A (en) * 1990-01-29 1991-01-29 International Business Machines Corporation Method of making bit stack compatible input/output circuits
JP2960560B2 (ja) 1991-02-28 1999-10-06 株式会社日立製作所 超小型電子機器
JP2855975B2 (ja) * 1992-07-06 1999-02-10 富士通株式会社 半導体集積回路
US5631842A (en) * 1995-03-07 1997-05-20 International Business Machines Corporation Parallel approach to chip wiring
JP3177464B2 (ja) * 1996-12-12 2001-06-18 株式会社日立製作所 入出力回路セル及び半導体集積回路装置
JP3380465B2 (ja) 1998-06-29 2003-02-24 松下電器産業株式会社 半導体装置
JP4330676B2 (ja) * 1998-08-17 2009-09-16 株式会社東芝 半導体集積回路
US6111310A (en) * 1998-09-30 2000-08-29 Lsi Logic Corporation Radially-increasing core power bus grid architecture
US6057596A (en) * 1998-10-19 2000-05-02 Silicon Integrated Systems Corp. Chip carrier having a specific power join distribution structure
KR100319883B1 (ko) * 1999-03-16 2002-01-10 윤종용 패드 주위에 더미 패턴을 구비한 반도체소자
US6446247B1 (en) 1999-11-29 2002-09-03 International Business Machines Corporation Optimization of printed wire circuitry on a single surface using a circle diameter
JP4535311B2 (ja) * 2003-02-27 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の配線構造
US11158566B2 (en) * 2019-05-24 2021-10-26 Google Llc Integrated circuit with a ring-shaped hot spot area and multidirectional cooling

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3558992A (en) * 1968-06-17 1971-01-26 Rca Corp Integrated circuit having bonding pads over unused active area components
US3751720A (en) * 1971-12-20 1973-08-07 Ibm Radially oriented monolithic circuit masterslice
JPS5378185A (en) * 1976-12-22 1978-07-11 Fujitsu Ltd Integrated circuit logical element
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
JPS58110063A (ja) * 1981-12-23 1983-06-30 Nec Corp 集積回路装置
JPS594050A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 半導体装置
JPS593950A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd ゲ−トアレイチツプ
JPS59197151A (ja) * 1983-04-22 1984-11-08 Toshiba Corp 半導体集積回路装置
JPS60121756A (ja) * 1983-12-06 1985-06-29 Toshiba Corp 半導体集積回路装置
JPS60144958A (ja) * 1984-01-09 1985-07-31 Nec Corp 相補型ｍｉｓ集積回路

Also Published As

Publication number Publication date
EP0219668A1 (de) 1987-04-29
CA1243424A (en) 1988-10-18
US4746966A (en) 1988-05-24
JPS6298746A (ja) 1987-05-08
JPH0573275B2 (de) 1993-10-14
EP0219668B1 (de) 1990-01-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee