DE3669797D1 - Datenverarbeitungssystem mit modulen, die zahlenfolgen auf steuerleitungen auf eine logische "oder"-weise kombinieren zur benutzung eines gemeinsam genutzten busses. - Google Patents

Datenverarbeitungssystem mit modulen, die zahlenfolgen auf steuerleitungen auf eine logische "oder"-weise kombinieren zur benutzung eines gemeinsam genutzten busses.

Info

Publication number
DE3669797D1
DE3669797D1 DE8686309174T DE3669797T DE3669797D1 DE 3669797 D1 DE3669797 D1 DE 3669797D1 DE 8686309174 T DE8686309174 T DE 8686309174T DE 3669797 T DE3669797 T DE 3669797T DE 3669797 D1 DE3669797 D1 DE 3669797D1
Authority
DE
Germany
Prior art keywords
control lines
logical
data processing
processing system
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686309174T
Other languages
English (en)
Inventor
George Tomomitsu Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE3669797D1 publication Critical patent/DE3669797D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
DE8686309174T 1985-12-02 1986-11-25 Datenverarbeitungssystem mit modulen, die zahlenfolgen auf steuerleitungen auf eine logische "oder"-weise kombinieren zur benutzung eines gemeinsam genutzten busses. Expired - Fee Related DE3669797D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/804,347 US4791562A (en) 1985-12-02 1985-12-02 Data processing system in which modules logically "OR" number sequences onto control lines to obtain the use of a time shared bus

Publications (1)

Publication Number Publication Date
DE3669797D1 true DE3669797D1 (de) 1990-04-26

Family

ID=25188746

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686309174T Expired - Fee Related DE3669797D1 (de) 1985-12-02 1986-11-25 Datenverarbeitungssystem mit modulen, die zahlenfolgen auf steuerleitungen auf eine logische "oder"-weise kombinieren zur benutzung eines gemeinsam genutzten busses.

Country Status (6)

Country Link
US (1) US4791562A (de)
EP (1) EP0227311B1 (de)
JP (1) JPS62134747A (de)
AT (1) ATE51310T1 (de)
CA (1) CA1277427C (de)
DE (1) DE3669797D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038274A (en) * 1987-11-23 1991-08-06 Digital Equipment Corporation Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus
US5127089A (en) * 1989-07-03 1992-06-30 Motorola, Inc. Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence
US5689657A (en) * 1991-03-30 1997-11-18 Deutsche Itt Industries Gmbh Apparatus and methods for bus arbitration in a multimaster system
US5307466A (en) * 1992-04-30 1994-04-26 International Business Machines Corporation Distributed programmable priority arbitration
US5948094A (en) * 1995-09-29 1999-09-07 Intel Corporation Method and apparatus for executing multiple transactions within a single arbitration cycle
US5842025A (en) * 1996-08-27 1998-11-24 Mmc Networks, Inc. Arbitration methods and apparatus
EP0858035B1 (de) * 1997-02-11 2005-04-13 Alcatel Auf Priorität basiertes Zugriffsteuerungsverfahren und -anordnung

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983540A (en) * 1975-09-08 1976-09-28 Honeywell Inc. Rapid bus priority resolution
CH607474A5 (de) * 1976-11-12 1978-12-29 Ibm
JPS5463634A (en) * 1977-10-03 1979-05-22 Nec Corp Bus controller
US4320502A (en) * 1978-02-22 1982-03-16 International Business Machines Corp. Distributed priority resolution system
US4320452A (en) * 1978-06-29 1982-03-16 Standard Oil Company (Indiana) Digital bus and control circuitry for data routing and transmission
US4281380A (en) * 1978-12-27 1981-07-28 Harris Corporation Bus collision avoidance system for distributed network data processing communications system
US4229792A (en) * 1979-04-09 1980-10-21 Honeywell Inc. Bus allocation synchronization system
US4334288A (en) * 1979-06-18 1982-06-08 Booher Robert K Priority determining network having user arbitration circuits coupled to a multi-line bus
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit
US4320467A (en) * 1980-02-25 1982-03-16 Raytheon Company Method and apparatus of bus arbitration using comparison of composite signals with device signals to determine device priority
US4323967A (en) * 1980-04-15 1982-04-06 Honeywell Information Systems Inc. Local bus interface for controlling information transfers between units in a central subsystem
NL8002344A (nl) 1980-04-23 1981-11-16 Philips Nv Multiprocessor systeem met gemeenschappelijke data/adres-bus.
US4468738A (en) * 1980-07-16 1984-08-28 Ford Aerospace & Communications Corporation Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors
JPS5725027A (en) * 1980-07-21 1982-02-09 Hitachi Ltd Data transmission controlling system of plural controllers
US4402040A (en) * 1980-09-24 1983-08-30 Raytheon Company Distributed bus arbitration method and apparatus
US4451881A (en) 1981-11-03 1984-05-29 International Business Machines Corp. Data processing system bus for multiple independent users
US4470112A (en) * 1982-01-07 1984-09-04 Bell Telephone Laboratories, Incorporated Circuitry for allocating access to a demand-shared bus
US4473880A (en) * 1982-01-26 1984-09-25 Intel Corporation Arbitration means for controlling access to a bus shared by a number of modules
US4516205A (en) * 1982-11-09 1985-05-07 Eing A Hubert I Access control of data transmission network
US4626843A (en) * 1983-09-27 1986-12-02 Trw Inc. Multi-master communication bus system with parallel bus request arbitration

Also Published As

Publication number Publication date
EP0227311A1 (de) 1987-07-01
JPS62134747A (ja) 1987-06-17
ATE51310T1 (de) 1990-04-15
CA1277427C (en) 1990-12-04
US4791562A (en) 1988-12-13
EP0227311B1 (de) 1990-03-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee