DE3676064D1 - Ausgangstreiber und steuerschaltung mit begrenzter stromaenderungsgeschwindigkeit. - Google Patents

Ausgangstreiber und steuerschaltung mit begrenzter stromaenderungsgeschwindigkeit.

Info

Publication number
DE3676064D1
DE3676064D1 DE8686202300T DE3676064T DE3676064D1 DE 3676064 D1 DE3676064 D1 DE 3676064D1 DE 8686202300 T DE8686202300 T DE 8686202300T DE 3676064 T DE3676064 T DE 3676064T DE 3676064 D1 DE3676064 D1 DE 3676064D1
Authority
DE
Germany
Prior art keywords
control switch
change speed
output driver
current change
limited current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686202300T
Other languages
English (en)
Inventor
Richard C Foss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3676064D1 publication Critical patent/DE3676064D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
    • H03K4/023—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators
DE8686202300T 1985-12-23 1986-12-16 Ausgangstreiber und steuerschaltung mit begrenzter stromaenderungsgeschwindigkeit. Expired - Lifetime DE3676064D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8531622A GB2184622B (en) 1985-12-23 1985-12-23 Outputbuffer and control circuit providing limited current rate at the output

Publications (1)

Publication Number Publication Date
DE3676064D1 true DE3676064D1 (de) 1991-01-17

Family

ID=10590180

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686202300T Expired - Lifetime DE3676064D1 (de) 1985-12-23 1986-12-16 Ausgangstreiber und steuerschaltung mit begrenzter stromaenderungsgeschwindigkeit.

Country Status (6)

Country Link
US (1) US4789796A (de)
EP (1) EP0228133B1 (de)
JP (1) JP2811176B2 (de)
KR (1) KR960008141B1 (de)
DE (1) DE3676064D1 (de)
GB (1) GB2184622B (de)

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US5293082A (en) * 1988-06-21 1994-03-08 Western Digital Corporation Output driver for reducing transient noise in integrated circuits
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JPH0777345B2 (ja) * 1988-11-04 1995-08-16 三菱電機株式会社 半導体装置
JPH0666674B2 (ja) * 1988-11-21 1994-08-24 株式会社東芝 半導体集積回路の出力回路
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US4962345A (en) * 1989-11-06 1990-10-09 Ncr Corporation Current limiting output driver
JP2671538B2 (ja) * 1990-01-17 1997-10-29 松下電器産業株式会社 入力バッファ回路
US5081374A (en) * 1990-02-22 1992-01-14 National Semiconductor Corporation Output buffer circuit with signal feed forward for reducing switching induced noise
US5097149A (en) * 1990-07-02 1992-03-17 Micron Technology, Inc. Two stage push-pull output buffer circuit with control logic feedback for reducing crossing current, switching noise and the like
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US5426376A (en) * 1993-04-23 1995-06-20 Vlsi Technology, Inc. Noise isolated I/O buffer that uses two separate power supplies
DE69407352T2 (de) * 1993-06-22 1998-06-04 Philips Electronics Nv Integrierter Schaltkreis mit Störsignal reduzierender Ausgangsstufe
EP0632591B1 (de) * 1993-06-22 1997-12-17 Koninklijke Philips Electronics N.V. Integrierter Schaltkreis mit Störsignal reduzierender Ausgangsstufe
US5438278A (en) * 1993-09-28 1995-08-01 Advanced Micro Devices, Inc. High speed CMOS output buffer circuit minimizes propagation delay and crowbar current
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US5859552A (en) * 1995-10-06 1999-01-12 Lsi Logic Corporation Programmable slew rate control circuit for output buffer
DE19604394A1 (de) * 1996-02-07 1997-08-14 Telefunken Microelectron Schaltungsanordnung zum Treiben einer Last
US5862390A (en) * 1996-03-15 1999-01-19 S3 Incorporated Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5656947A (en) * 1996-07-16 1997-08-12 National Semiconductor Corporation Low noise digital output buffer
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5917758A (en) 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US5940608A (en) * 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) * 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US5898638A (en) * 1997-03-11 1999-04-27 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US5870347A (en) 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US5929680A (en) * 1997-05-16 1999-07-27 Tritech Microelectronics International Ltd Short circuit reduced CMOS buffer circuit
US6014759A (en) * 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5926047A (en) * 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6051995A (en) * 1998-09-11 2000-04-18 Sharp Electronics Corporation Constant impedance, low noise CMOS buffer
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US7069406B2 (en) 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
DE19932944B4 (de) * 1999-07-14 2005-10-20 Infineon Technologies Ag Schaltungsanordnung zum Ansteuern einer Last
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6529050B1 (en) * 2001-08-20 2003-03-04 National Semiconductor Corporation High-speed clock buffer that has a substantially reduced crowbar current
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
JP2009021651A (ja) * 2007-07-10 2009-01-29 Nec Electronics Corp 出力バッファ回路
TW201032476A (en) * 2009-02-18 2010-09-01 Etron Technology Inc Signal converting device
US9647559B2 (en) * 2015-01-26 2017-05-09 Infineon Technologies Americas Corp. Circuit implementations reducing losses in a power supply
US10735000B1 (en) 2019-12-19 2020-08-04 Globalfoundries Inc. Pre-driver circuits for an output driver
US11005454B1 (en) 2019-12-19 2021-05-11 Globalfoundries U.S. Inc. Pre-driver circuits for an output driver

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JPS58188931A (ja) * 1982-04-28 1983-11-04 Seiko Epson Corp Ｃｍｏｓバツファアンプ駆動回路
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US4567379A (en) * 1984-05-23 1986-01-28 Burroughs Corporation Parallel current sharing system
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JP3844541B2 (ja) * 1996-06-17 2006-11-15 株式会社シマノ 振出竿

Also Published As

Publication number Publication date
GB2184622A (en) 1987-06-24
KR870006701A (ko) 1987-07-14
US4789796A (en) 1988-12-06
KR960008141B1 (ko) 1996-06-20
JP2811176B2 (ja) 1998-10-15
GB2184622B (en) 1989-10-18
JPS62159514A (ja) 1987-07-15
EP0228133A1 (de) 1987-07-08
GB8531622D0 (en) 1986-02-05
EP0228133B1 (de) 1990-12-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee