DE3683477D1 - Scheibenbereichsschaltungsintegrierter speicher. - Google Patents

Scheibenbereichsschaltungsintegrierter speicher.

Info

Publication number
DE3683477D1
DE3683477D1 DE8686904285T DE3683477T DE3683477D1 DE 3683477 D1 DE3683477 D1 DE 3683477D1 DE 8686904285 T DE8686904285 T DE 8686904285T DE 3683477 T DE3683477 T DE 3683477T DE 3683477 D1 DE3683477 D1 DE 3683477D1
Authority
DE
Germany
Prior art keywords
pct
modules
memory
read
transmit path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686904285T
Other languages
English (en)
Inventor
Michael Brent
Neal Macdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anamartic Ltd
Original Assignee
Anamartic Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB8517699A external-priority patent/GB2177825B/en
Application filed by Anamartic Ltd filed Critical Anamartic Ltd
Application granted granted Critical
Publication of DE3683477D1 publication Critical patent/DE3683477D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
DE8686904285T 1985-07-12 1986-07-11 Scheibenbereichsschaltungsintegrierter speicher. Expired - Fee Related DE3683477D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB8517699A GB2177825B (en) 1985-07-12 1985-07-12 Control system for chained circuit modules
GB08525324A GB2178204B (en) 1985-07-12 1985-10-15 Wafer-scale integrated circuit memory
PCT/GB1986/000400 WO1987000674A2 (en) 1985-07-12 1986-07-11 Wafer-scale integrated circuit memory

Publications (1)

Publication Number Publication Date
DE3683477D1 true DE3683477D1 (de) 1992-02-27

Family

ID=26289520

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686904285T Expired - Fee Related DE3683477D1 (de) 1985-07-12 1986-07-11 Scheibenbereichsschaltungsintegrierter speicher.

Country Status (5)

Country Link
US (1) US5072424A (de)
EP (1) EP0229144B1 (de)
AT (1) ATE71762T1 (de)
DE (1) DE3683477D1 (de)
WO (1) WO1987000674A2 (de)

Families Citing this family (40)

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US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
GB8825780D0 (en) * 1988-11-03 1988-12-07 Microcomputer Tech Serv Digital computer
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
US6009501A (en) * 1997-06-18 1999-12-28 Micron Technology, Inc. Method and apparatus for local control signal generation in a memory device
US6032220A (en) * 1997-07-18 2000-02-29 Micron Technology, Inc. Memory device with dual timing and signal latching control
KR20050022798A (ko) * 2003-08-30 2005-03-08 주식회사 이즈텍 유전자 어휘 분류체계를 이용하여 바이오 칩을 분석하기위한 시스템 및 그 방법
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
JPS599117B2 (ja) * 1977-04-11 1984-02-29 日本電気株式会社 記憶装置
US4316264A (en) * 1980-01-08 1982-02-16 Eliyahou Harari Uniquely accessed RAM
GB2128382B (en) * 1980-08-21 1984-10-10 Burroughs Corp Conditionally-powered cells including wafer scale integrated circuit
GB2089536B (en) * 1980-12-12 1984-05-23 Burroughs Corp Improvement in or relating to wafer scale integrated circuits
JPH0762958B2 (ja) * 1983-06-03 1995-07-05 株式会社日立製作所 Ｍｏｓ記憶装置
US4646270A (en) * 1983-09-15 1987-02-24 Motorola, Inc. Video graphic dynamic RAM
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element

Also Published As

Publication number Publication date
ATE71762T1 (de) 1992-02-15
EP0229144B1 (de) 1992-01-15
WO1987000674A2 (en) 1987-01-29
EP0229144A1 (de) 1987-07-22
WO1987000674A3 (en) 1987-03-26
US5072424A (en) 1991-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee