DE3686902D1 - Selbstpruefender zweikanal-anstiegsflanken-synchronisierer. - Google Patents

Selbstpruefender zweikanal-anstiegsflanken-synchronisierer.

Info

Publication number
DE3686902D1
DE3686902D1 DE8686303561T DE3686902T DE3686902D1 DE 3686902 D1 DE3686902 D1 DE 3686902D1 DE 8686303561 T DE8686303561 T DE 8686303561T DE 3686902 T DE3686902 T DE 3686902T DE 3686902 D1 DE3686902 D1 DE 3686902D1
Authority
DE
Germany
Prior art keywords
flip
circuit
synchronizer
flop
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686303561T
Other languages
English (en)
Other versions
DE3686902T2 (de
Inventor
Srikumar R Chandran
Mark S Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Application granted granted Critical
Publication of DE3686902D1 publication Critical patent/DE3686902D1/de
Publication of DE3686902T2 publication Critical patent/DE3686902T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
DE8686303561T 1985-05-10 1986-05-09 Selbstpruefender zweikanal-anstiegsflanken-synchronisierer. Expired - Lifetime DE3686902T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/733,293 US4700346A (en) 1985-05-10 1985-05-10 Self-checking, dual railed, leading edge synchronizer

Publications (2)

Publication Number Publication Date
DE3686902D1 true DE3686902D1 (de) 1992-11-12
DE3686902T2 DE3686902T2 (de) 1993-02-18

Family

ID=24947021

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686303561T Expired - Lifetime DE3686902T2 (de) 1985-05-10 1986-05-09 Selbstpruefender zweikanal-anstiegsflanken-synchronisierer.

Country Status (9)

Country Link
US (1) US4700346A (de)
EP (1) EP0202085B1 (de)
JP (1) JPS6231440A (de)
AT (1) ATE81427T1 (de)
AU (1) AU566221B2 (de)
CA (1) CA1253926A (de)
DE (1) DE3686902T2 (de)
MX (1) MX164336B (de)
NO (1) NO171617C (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU568977B2 (en) 1985-05-10 1988-01-14 Tandem Computers Inc. Dual processor error detection system
FR2608863B1 (fr) * 1986-12-19 1994-04-29 Nec Corp Circuit integre logique comportant des bascules electroniques d'entree et de sortie pour stabiliser les durees des impulsions
US4821295A (en) * 1987-11-30 1989-04-11 Tandem Computers Incorporated Two-stage synchronizer
US5117442A (en) * 1988-12-14 1992-05-26 National Semiconductor Corporation Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system
EP0379279A3 (de) * 1989-01-17 1991-09-11 Marconi Instruments Limited Datenvermittlungssynchronisator
US5128947A (en) * 1989-06-30 1992-07-07 Motorola, Inc. Self-checking memory cell array apparatus
US5032743A (en) * 1990-05-09 1991-07-16 National Semiconductor Corporation Skew clamp
US5384781A (en) * 1991-02-11 1995-01-24 Tektronix, Inc. Automatic skew calibration for multi-channel signal sources
US5260952A (en) * 1991-04-30 1993-11-09 Ibm Corporation Fault tolerant logic system
US6097775A (en) * 1998-02-17 2000-08-01 Lsi Logic Corporation Method and apparatus for synchronously transferring signals between clock domains
US6173351B1 (en) * 1998-06-15 2001-01-09 Sun Microsystems, Inc. Multi-processor system bridge
US6617901B1 (en) 2001-04-27 2003-09-09 Cypress Semiconductor Corp. Master/dual-slave D type flip-flop
US7506293B2 (en) * 2006-03-22 2009-03-17 Synopsys, Inc. Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis
US11025240B2 (en) * 2016-12-14 2021-06-01 Mediatek Inc. Circuits for delay mismatch compensation and related methods
KR102617240B1 (ko) * 2017-02-28 2023-12-27 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE788129A (fr) * 1971-08-30 1973-02-28 Siemens Ag Element de memoire electronique pour installations de traitement de donnees digitales a haute fiabilite en particulier pourle service de securite ferroviaire
DE2938228C2 (de) * 1979-09-21 1982-02-25 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren und Schaltung zur Synchronisation
US4328583A (en) * 1980-09-08 1982-05-04 Rockwell International Corporation Data bus fault detector
US4342112A (en) * 1980-09-08 1982-07-27 Rockwell International Corporation Error checking circuit
JPS5854756A (ja) * 1981-09-28 1983-03-31 Hitachi Ltd 多重伝送システムの信号診断方法およびその診断装置
US4525635A (en) * 1982-12-15 1985-06-25 Rca Corporation Transient signal suppression circuit
US4551836A (en) * 1983-06-22 1985-11-05 Gte Automatic Electric Incorporated Cross-copy arrangement for synchronizing error detection clock signals in a duplex digital system
US4589066A (en) * 1984-05-31 1986-05-13 General Electric Company Fault tolerant, frame synchronization for multiple processor systems

Also Published As

Publication number Publication date
JPS6231440A (ja) 1987-02-10
EP0202085B1 (de) 1992-10-07
US4700346A (en) 1987-10-13
MX164336B (es) 1992-08-04
DE3686902T2 (de) 1993-02-18
JPH04303B2 (de) 1992-01-07
CA1253926A (en) 1989-05-09
NO171617B (no) 1992-12-28
EP0202085A2 (de) 1986-11-20
AU566221B2 (en) 1987-10-15
NO861862L (no) 1986-11-11
AU5720386A (en) 1986-11-13
EP0202085A3 (en) 1988-03-16
NO171617C (no) 1993-04-07
ATE81427T1 (de) 1992-10-15

Similar Documents

Publication Publication Date Title
DE3686902D1 (de) Selbstpruefender zweikanal-anstiegsflanken-synchronisierer.
SE8405090L (sv) Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets
AU1082099A (en) Method and apparatus for coupling signals between two circuits operating in different clock domains
TW373368B (en) Separate set/reset paths for time critical signals
JPH03237832A (ja) データ・クロックのタイミング合わせ回路
KR920007138A (ko) 프로세스 모니터 회로 및 그 방법
KR840004282A (ko) 동기회로
EP0344426A3 (de) Selbstprüfende Majoritätsvotumlogik für fehlertolerante Rechnungsanwendungen
CA2096628A1 (en) Clock phase alignment
ATE61176T1 (de) In integrierter technik hergestellter baustein zur erstellung integrierter schaltungen.
US5249214A (en) Low skew CMOS clock divider
GB1312401A (en) Shift register systems
GB1368585A (en) Device for the digital subtraction of frequencies
DE3881220D1 (de) Kommunikationsvermittlungselement.
SU1644147A1 (ru) Мажоритарно-резервированное устройство
MY104382A (en) Signal synchronizing system.
DK160476C (da) Fremgangsmaade til fremstilling af en kasse, samt indretning for fast men aftageligt at forbinde et kantparti for en foerste del med et kantparti for en anden del
JPS63254827A (ja) デコ−ド回路
SU849419A1 (ru) Цифровой частотный дискриминатор
SU1325454A1 (ru) Многоканальное устройство дл сдвига во времени совпадающих импульсов
JPS6048775B2 (ja) 物理機番の認識方法
JPS6450144A (en) Memory checking system
JPS6349933B2 (de)
JPS5761328A (en) Detection circuit of coincidence of changing point of two kinds of clock signal
SE9203882D0 (sv) Saett och anordning foer minimering av scew

Legal Events

Date Code Title Description
8364 No opposition during term of opposition