DE3688978T2 - Seitenspeicherverwaltungseinheit mit der fähigkeit nach wahl mehrere adressräume zu unterstützen. - Google Patents

Seitenspeicherverwaltungseinheit mit der fähigkeit nach wahl mehrere adressräume zu unterstützen.

Info

Publication number
DE3688978T2
DE3688978T2 DE86907117T DE3688978T DE3688978T2 DE 3688978 T2 DE3688978 T2 DE 3688978T2 DE 86907117 T DE86907117 T DE 86907117T DE 3688978 T DE3688978 T DE 3688978T DE 3688978 T2 DE3688978 T2 DE 3688978T2
Authority
DE
Germany
Prior art keywords
ability
management unit
storage management
support multiple
page storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86907117T
Other languages
English (en)
Other versions
DE3688978D1 (de
Inventor
William Moyer
Michael Cruess
William Keshlear
John Zolnowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE3688978D1 publication Critical patent/DE3688978D1/de
Publication of DE3688978T2 publication Critical patent/DE3688978T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
DE86907117T 1986-01-15 1986-11-06 Seitenspeicherverwaltungseinheit mit der fähigkeit nach wahl mehrere adressräume zu unterstützen. Expired - Fee Related DE3688978T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/819,180 US4763244A (en) 1986-01-15 1986-01-15 Paged memory management unit capable of selectively supporting multiple address spaces

Publications (2)

Publication Number Publication Date
DE3688978D1 DE3688978D1 (de) 1993-10-07
DE3688978T2 true DE3688978T2 (de) 1994-01-20

Family

ID=25227414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86907117T Expired - Fee Related DE3688978T2 (de) 1986-01-15 1986-11-06 Seitenspeicherverwaltungseinheit mit der fähigkeit nach wahl mehrere adressräume zu unterstützen.

Country Status (6)

Country Link
US (2) US4763244A (de)
EP (1) EP0253824B1 (de)
JP (1) JP2567594B2 (de)
KR (1) KR940011668B1 (de)
DE (1) DE3688978T2 (de)
WO (1) WO1987004544A1 (de)

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US5640528A (en) * 1991-10-24 1997-06-17 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers
US5627987A (en) * 1991-11-29 1997-05-06 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5696925A (en) * 1992-02-25 1997-12-09 Hyundai Electronics Industries, Co., Ltd. Memory management unit with address translation function
JP2839060B2 (ja) * 1992-03-02 1998-12-16 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システムおよびデータ処理方法
US5493661A (en) * 1992-03-06 1996-02-20 International Business Machines Corporation Method and system for providing a program call to a dispatchable unit's base space
WO1993018461A1 (en) * 1992-03-09 1993-09-16 Auspex Systems, Inc. High-performance non-volatile ram protected write cache accelerator system
US5555395A (en) * 1993-05-28 1996-09-10 Dell U.S.A. L.P. System for memory table cache reloads in a reduced number of cycles using a memory controller to set status bits in the main memory table
US5682495A (en) * 1994-12-09 1997-10-28 International Business Machines Corporation Fully associative address translation buffer having separate segment and page invalidation
US5752275A (en) * 1995-03-31 1998-05-12 Intel Corporation Translation look-aside buffer including a single page size translation unit
US5724604A (en) * 1995-08-02 1998-03-03 Motorola, Inc. Data processing system for accessing an external device and method therefor
US5802541A (en) * 1996-02-28 1998-09-01 Motorola, Inc. Method and apparatus in a data processing system for using chip selects to perform a memory management function
US5914730A (en) * 1997-09-09 1999-06-22 Compaq Computer Corp. System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests
US6249906B1 (en) * 1998-06-26 2001-06-19 International Business Machines Corp. Adaptive method and system to minimize the effect of long table walks
EP1471421A1 (de) * 2003-04-24 2004-10-27 STMicroelectronics Limited Steuerung für spekulativen Ladebefehl
US8516300B2 (en) * 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US20070050605A1 (en) * 2005-08-29 2007-03-01 Bran Ferren Freeze-dried ghost pages
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US7607042B2 (en) * 2005-08-29 2009-10-20 Searete, Llc Adjusting a processor operating parameter based on a performance criterion
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US8209524B2 (en) * 2005-08-29 2012-06-26 The Invention Science Fund I, Llc Cross-architecture optimization
US7725693B2 (en) * 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US7739524B2 (en) * 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US7539852B2 (en) 2005-08-29 2009-05-26 Searete, Llc Processor resource management
US7779213B2 (en) * 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US8255745B2 (en) * 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US8402257B2 (en) * 2005-08-29 2013-03-19 The Invention Science Fund I, PLLC Alteration of execution of a program in response to an execution-optimization information
US7644251B2 (en) * 2005-12-19 2010-01-05 Sigmatel, Inc. Non-volatile solid-state memory controller
US7376807B2 (en) * 2006-02-23 2008-05-20 Freescale Semiconductor, Inc. Data processing system having address translation bypass and method therefor
US7401201B2 (en) * 2006-04-28 2008-07-15 Freescale Semiconductor, Inc. Processor and method for altering address translation
US9697211B1 (en) * 2006-12-01 2017-07-04 Synopsys, Inc. Techniques for creating and using a hierarchical data structure
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
TWI492051B (zh) * 2012-09-05 2015-07-11 Silicon Motion Inc 資料儲存裝置與快閃記憶體控制方法
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

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Also Published As

Publication number Publication date
KR880700972A (ko) 1988-04-13
EP0253824A4 (de) 1990-03-21
EP0253824A1 (de) 1988-01-27
JP2567594B2 (ja) 1996-12-25
US4763244A (en) 1988-08-09
DE3688978D1 (de) 1993-10-07
US4800489A (en) 1989-01-24
WO1987004544A1 (en) 1987-07-30
EP0253824B1 (de) 1993-09-01
KR940011668B1 (ko) 1994-12-23
JPS63502224A (ja) 1988-08-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee