DE3689217D1 - Datenverarbeitungseinrichtung mit einer Schaltung zur Prüfung der Adressgrenzen in einem virtuellen Speicher. - Google Patents

Datenverarbeitungseinrichtung mit einer Schaltung zur Prüfung der Adressgrenzen in einem virtuellen Speicher.

Info

Publication number
DE3689217D1
DE3689217D1 DE86111162T DE3689217T DE3689217D1 DE 3689217 D1 DE3689217 D1 DE 3689217D1 DE 86111162 T DE86111162 T DE 86111162T DE 3689217 T DE3689217 T DE 3689217T DE 3689217 D1 DE3689217 D1 DE 3689217D1
Authority
DE
Germany
Prior art keywords
checking
circuit
data processing
processing device
virtual memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86111162T
Other languages
English (en)
Other versions
DE3689217T2 (de
Inventor
Toyohiko Kagimasa
Kikuo Takahashi
Yoshie Ono
Seiichi Yoshizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3689217D1 publication Critical patent/DE3689217D1/de
Application granted granted Critical
Publication of DE3689217T2 publication Critical patent/DE3689217T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
DE86111162T 1985-09-06 1986-08-12 Datenverarbeitungseinrichtung mit einer Schaltung zur Prüfung der Adressgrenzen in einem virtuellen Speicher. Expired - Fee Related DE3689217T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60195842A JPH0782458B2 (ja) 1985-09-06 1985-09-06 データ処理装置

Publications (2)

Publication Number Publication Date
DE3689217D1 true DE3689217D1 (de) 1993-12-02
DE3689217T2 DE3689217T2 (de) 1994-02-24

Family

ID=16347912

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86111162T Expired - Fee Related DE3689217T2 (de) 1985-09-06 1986-08-12 Datenverarbeitungseinrichtung mit einer Schaltung zur Prüfung der Adressgrenzen in einem virtuellen Speicher.

Country Status (4)

Country Link
US (1) US4851989A (de)
EP (1) EP0214490B1 (de)
JP (1) JPH0782458B2 (de)
DE (1) DE3689217T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104868B2 (ja) * 1988-04-08 1995-11-13 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン データ記憶検索システム
US5555387A (en) * 1995-06-06 1996-09-10 International Business Machines Corporation Method and apparatus for implementing virtual memory having multiple selected page sizes
US5784713A (en) * 1993-03-05 1998-07-21 Cyrix Corporation Address calculation logic including limit checking using carry out to flag limit violation
US5590351A (en) * 1994-01-21 1996-12-31 Advanced Micro Devices, Inc. Superscalar execution unit for sequential instruction pointer updates and segment limit checks
US5564030A (en) * 1994-02-08 1996-10-08 Meridian Semiconductor, Inc. Circuit and method for detecting segment limit errors for code fetches
US5577219A (en) * 1994-05-02 1996-11-19 Intel Corporation Method and apparatus for preforming memory segment limit violation checks
US5513337A (en) * 1994-05-25 1996-04-30 Intel Corporation System for protecting unauthorized memory accesses by comparing base memory address with mask bits and having attribute bits for identifying access operational mode and type
WO1996008775A1 (en) * 1994-09-16 1996-03-21 Philips Electronics N.V. Software programmable bus disable system
US5822786A (en) * 1994-11-14 1998-10-13 Advanced Micro Devices, Inc. Apparatus and method for determining if an operand lies within an expand up or expand down segment
US5701448A (en) * 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
EP0976050B1 (de) * 1996-01-24 2002-06-12 Sun Microsystems, Inc. Prozessor mit Bereichsüberprüfung bei Matrixzugriffen
FR2766597B1 (fr) * 1997-07-23 2004-01-09 Inside Technologies Microprocesseur comportant un chemin d'adresses securise
KR101724590B1 (ko) * 2011-01-31 2017-04-11 삼성전자주식회사 멀티 프로세서 시스템에서의 메모리 보호 장치 및 방법
CN112860174A (zh) * 2019-11-27 2021-05-28 瑞昱半导体股份有限公司 数据写入系统与方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2258112A5 (de) * 1973-11-30 1975-08-08 Honeywell Bull Soc Ind
FR2253424A5 (en) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second
US4084227A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
GB2059652B (en) * 1979-09-29 1983-08-24 Plessey Co Ltd Memory protection system using capability registers
US4584666A (en) * 1984-06-21 1986-04-22 Motorola, Inc. Method and apparatus for signed and unsigned bounds check

Also Published As

Publication number Publication date
EP0214490B1 (de) 1993-10-27
JPH0782458B2 (ja) 1995-09-06
EP0214490A3 (en) 1990-01-10
DE3689217T2 (de) 1994-02-24
EP0214490A2 (de) 1987-03-18
US4851989A (en) 1989-07-25
JPS6257044A (ja) 1987-03-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee