DE3750028T2 - Pipelineprozessor mit schwacher Kopplung. - Google Patents

Pipelineprozessor mit schwacher Kopplung.

Info

Publication number
DE3750028T2
DE3750028T2 DE3750028T DE3750028T DE3750028T2 DE 3750028 T2 DE3750028 T2 DE 3750028T2 DE 3750028 T DE3750028 T DE 3750028T DE 3750028 T DE3750028 T DE 3750028T DE 3750028 T2 DE3750028 T2 DE 3750028T2
Authority
DE
Germany
Prior art keywords
weak coupling
pipeline processor
pipeline
processor
weak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3750028T
Other languages
English (en)
Other versions
DE3750028D1 (de
Inventor
Tokuzo Kiyohara
Masashi Deguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE3750028D1 publication Critical patent/DE3750028D1/de
Application granted granted Critical
Publication of DE3750028T2 publication Critical patent/DE3750028T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
DE3750028T 1986-12-29 1987-12-28 Pipelineprozessor mit schwacher Kopplung. Expired - Fee Related DE3750028T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61311023A JP2695157B2 (ja) 1986-12-29 1986-12-29 可変パイプラインプロセッサ

Publications (2)

Publication Number Publication Date
DE3750028D1 DE3750028D1 (de) 1994-07-14
DE3750028T2 true DE3750028T2 (de) 1994-10-06

Family

ID=18012186

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750028T Expired - Fee Related DE3750028T2 (de) 1986-12-29 1987-12-28 Pipelineprozessor mit schwacher Kopplung.

Country Status (5)

Country Link
US (1) US4967338A (de)
EP (1) EP0272705B1 (de)
JP (1) JP2695157B2 (de)
KR (1) KR910006144B1 (de)
DE (1) DE3750028T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
IL92605A0 (en) * 1988-12-19 1990-08-31 Bull Hn Information Syst Production line method and apparatus for high performance instruction execution
US5109495A (en) * 1989-02-03 1992-04-28 Digital Equipment Corp. Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor
JP2538053B2 (ja) * 1989-05-08 1996-09-25 松下電器産業株式会社 制御装置
US5150468A (en) * 1989-06-30 1992-09-22 Bull Hn Information Systems Inc. State controlled instruction logic management apparatus included in a pipelined processing unit
JPH04260929A (ja) * 1991-01-21 1992-09-16 Mitsubishi Electric Corp データ処理装置
JPH04340145A (ja) * 1991-05-17 1992-11-26 Nec Corp キャッシュメモリ装置
US5546593A (en) * 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
US6240508B1 (en) * 1992-07-06 2001-05-29 Compaq Computer Corporation Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read
US5706459A (en) * 1994-01-06 1998-01-06 Fujitsu Limited Processor having a variable number of stages in a pipeline
AUPO648397A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6311258B1 (en) 1997-04-03 2001-10-30 Canon Kabushiki Kaisha Data buffer apparatus and method for storing graphical data using data encoders and decoders
JP2944563B2 (ja) * 1997-04-03 1999-09-06 甲府日本電気株式会社 パイプライン型情報処理装置
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US5978871A (en) * 1997-04-14 1999-11-02 International Business Machines Corporation Method of layering cache and architectural specific functions for operation splitting
US6259456B1 (en) 1997-04-30 2001-07-10 Canon Kabushiki Kaisha Data normalization techniques
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6507898B1 (en) 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US20050240806A1 (en) * 2004-03-30 2005-10-27 Hewlett-Packard Development Company, L.P. Diagnostic memory dump method in a redundant processor
CN102681796B (zh) * 2012-05-18 2015-04-08 重庆大学 数据多级流水算法模块中的ram分布结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342078A (en) * 1979-05-21 1982-07-27 Motorola, Inc. Instruction register sequence decoder for microprogrammed data processor and method
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
JPS5890247A (ja) * 1981-11-25 1983-05-28 Nippon Telegr & Teleph Corp <Ntt> 情報処理装置のパイプライン制御方式
US4597041A (en) * 1982-11-15 1986-06-24 Data General Corp. Method and apparatus for enhancing the operation of a data processing system
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
JPS60129837A (ja) * 1983-12-19 1985-07-11 Matsushita Electric Ind Co Ltd 信号処理演算プロセツサ
JPS60186936A (ja) * 1984-03-05 1985-09-24 Hitachi Ltd プログラマブルコントロ−ラ
US4739472A (en) * 1984-12-07 1988-04-19 Nec Corporation Information processing device capable of rapidly processing instructions of different groups
IT1275935B1 (it) * 1995-03-17 1997-10-24 Chiesi Farma Spa Derivato di aminotetralina per la terapia di malattie cardiovascolari

Also Published As

Publication number Publication date
EP0272705B1 (de) 1994-06-08
EP0272705A3 (en) 1990-12-19
DE3750028D1 (de) 1994-07-14
EP0272705A2 (de) 1988-06-29
KR880008150A (ko) 1988-08-30
JP2695157B2 (ja) 1997-12-24
JPS63167935A (ja) 1988-07-12
KR910006144B1 (ko) 1991-08-16
US4967338A (en) 1990-10-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee