DE3750169T2 - Verfahren zum Ebnen eines Halbleitersubstrates. - Google Patents

Verfahren zum Ebnen eines Halbleitersubstrates.

Info

Publication number
DE3750169T2
DE3750169T2 DE3750169T DE3750169T DE3750169T2 DE 3750169 T2 DE3750169 T2 DE 3750169T2 DE 3750169 T DE3750169 T DE 3750169T DE 3750169 T DE3750169 T DE 3750169T DE 3750169 T2 DE3750169 T2 DE 3750169T2
Authority
DE
Germany
Prior art keywords
leveling
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3750169T
Other languages
English (en)
Other versions
DE3750169D1 (de
Inventor
Paul E Riley
Alan B Ray
Paul Bayer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Application granted granted Critical
Publication of DE3750169D1 publication Critical patent/DE3750169D1/de
Publication of DE3750169T2 publication Critical patent/DE3750169T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE3750169T 1986-04-23 1987-04-23 Verfahren zum Ebnen eines Halbleitersubstrates. Expired - Lifetime DE3750169T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/855,207 US4676868A (en) 1986-04-23 1986-04-23 Method for planarizing semiconductor substrates

Publications (2)

Publication Number Publication Date
DE3750169D1 DE3750169D1 (de) 1994-08-11
DE3750169T2 true DE3750169T2 (de) 1995-02-02

Family

ID=25320612

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750169T Expired - Lifetime DE3750169T2 (de) 1986-04-23 1987-04-23 Verfahren zum Ebnen eines Halbleitersubstrates.

Country Status (4)

Country Link
US (1) US4676868A (de)
EP (1) EP0243273B1 (de)
JP (1) JPS6323337A (de)
DE (1) DE3750169T2 (de)

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US4816112A (en) * 1986-10-27 1989-03-28 International Business Machines Corporation Planarization process through silylation
US4867838A (en) * 1986-10-27 1989-09-19 International Business Machines Corporation Planarization through silylation
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection
GB8729652D0 (en) * 1987-12-19 1988-02-03 Plessey Co Plc Semi-conductive devices fabricated on soi wafers
DE3801976A1 (de) * 1988-01-23 1989-08-03 Telefunken Electronic Gmbh Verfahren zum planarisieren von halbleiteroberflaechen
JPH01212439A (ja) * 1988-02-19 1989-08-25 Nippon Telegr & Teleph Corp <Ntt> 層間膜の加工法
FR2627902B1 (fr) * 1988-02-26 1990-06-22 Philips Nv Procede pour aplanir la surface d'un dispositif semiconducteur
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
JPH01296611A (ja) * 1988-05-25 1989-11-30 Canon Inc 半導体薄膜堆積法
US4952274A (en) * 1988-05-27 1990-08-28 Northern Telecom Limited Method for planarizing an insulating layer
EP0372644B1 (de) * 1988-12-09 1995-05-03 Laboratoires D'electronique Philips Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten
US5014217A (en) * 1989-02-09 1991-05-07 S C Technology, Inc. Apparatus and method for automatically identifying chemical species within a plasma reactor environment
US4946547A (en) * 1989-10-13 1990-08-07 Cree Research, Inc. Method of preparing silicon carbide surfaces for crystal growth
US5208176A (en) * 1990-01-16 1993-05-04 Micron Technology, Inc. Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization
US4986876A (en) * 1990-05-07 1991-01-22 The United States Of America As Represented By The Secretary Of The Army Method of smoothing patterned transparent electrode stripes in thin film electroluminescent display panel manufacture
US5215933A (en) * 1990-05-11 1993-06-01 Kabushiki Kaisha Toshiba Method of manufacturing nonvolatile semiconductor memory device
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
US5139608A (en) * 1991-04-01 1992-08-18 Motorola, Inc. Method of planarizing a semiconductor device surface
JP2913918B2 (ja) * 1991-08-26 1999-06-28 日本電気株式会社 半導体装置の製造方法
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product
US5877032A (en) * 1995-10-12 1999-03-02 Lucent Technologies Inc. Process for device fabrication in which the plasma etch is controlled by monitoring optical emission
US5469200A (en) * 1991-11-12 1995-11-21 Canon Kabushiki Kaisha Polycrystalline silicon substrate having a thermally-treated surface, and process of making the same
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
US5346862A (en) * 1992-06-22 1994-09-13 Siemens Aktiengesellschaft Method for the electrical insulation of a circuit function element on a semiconductor component
US5347460A (en) * 1992-08-25 1994-09-13 International Business Machines Corporation Method and system employing optical emission spectroscopy for monitoring and controlling semiconductor fabrication
US5272117A (en) * 1992-12-07 1993-12-21 Motorola, Inc. Method for planarizing a layer of material
US5372673A (en) * 1993-01-25 1994-12-13 Motorola, Inc. Method for processing a layer of material while using insitu monitoring and control
US5546322A (en) * 1994-04-12 1996-08-13 International Business Machines Corporation Method and system for analyzing plasma data
DE4434891B4 (de) * 1994-09-29 2005-01-05 Infineon Technologies Ag Verfahren zum Freilegen einer oberen Stegfläche eines auf der Oberfläche eines Substrats ausgebildeten und mit einem Material umformten schmalen Steges im Mikrometerbereich und Anwendung eines solchen Verfahrens zur Kontaktierung schmaler Stege
US5679610A (en) * 1994-12-15 1997-10-21 Kabushiki Kaisha Toshiba Method of planarizing a semiconductor workpiece surface
JP3355851B2 (ja) * 1995-03-07 2002-12-09 株式会社デンソー 絶縁ゲート型電界効果トランジスタ及びその製造方法
US5962903A (en) * 1995-06-08 1999-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized plug-diode mask ROM structure
JPH09167753A (ja) * 1995-08-14 1997-06-24 Toshiba Corp 半導体基板の表面の平坦化方法とその装置
JPH0964037A (ja) * 1995-08-23 1997-03-07 Mitsubishi Electric Corp 半導体装置の製造方法
US5783488A (en) * 1996-01-31 1998-07-21 Vlsi Technology, Inc. Optimized underlayer structures for maintaining chemical mechanical polishing removal rates
US5858876A (en) * 1996-04-01 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
JPH1140664A (ja) * 1997-07-17 1999-02-12 Mitsubishi Electric Corp 半導体装置の製造方法
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
US6440644B1 (en) 1997-10-15 2002-08-27 Kabushiki Kaisha Toshiba Planarization method and system using variable exposure
DE19753782A1 (de) * 1997-12-04 1999-06-10 Inst Halbleiterphysik Gmbh Verfahren zur Planarisierung von Silizium-Wafern
US6168972B1 (en) 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
EP1071121A1 (de) * 1999-07-19 2001-01-24 International Business Machines Corporation Verfahren zur Herstellung einer Oxid-Ummantelung in einem Graben in einem Halbleitersubstrat
IE20000440A1 (en) * 2000-05-31 2003-04-02 Loctite R & D Ltd Semi-Solid one- or two-part compositions
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US20050161814A1 (en) * 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
JP2004212933A (ja) * 2002-12-31 2004-07-29 Lg Phillips Lcd Co Ltd 液晶表示装置及びアレイ基板の製造方法
US7300595B2 (en) * 2003-12-25 2007-11-27 Tdk Corporation Method for filling concave portions of concavo-convex pattern and method for manufacturing magnetic recording medium
JP4775806B2 (ja) * 2004-02-10 2011-09-21 Ｔｄｋ株式会社 磁気記録媒体の製造方法
JP4008420B2 (ja) * 2004-02-23 2007-11-14 Ｔｄｋ株式会社 磁気記録媒体の製造方法
US7501299B2 (en) * 2005-11-14 2009-03-10 Palo Alto Research Center Incorporated Method for controlling the structure and surface qualities of a thin film and product produced thereby
US20090053845A1 (en) * 2005-11-14 2009-02-26 Palo Alto Research Center Incorporated Method For Controlling The Structure And Surface Qualities Of A Thin Film And Product Produced Thereby
US7906058B2 (en) * 2005-12-01 2011-03-15 Molecular Imprints, Inc. Bifurcated contact printing technique
US7803308B2 (en) * 2005-12-01 2010-09-28 Molecular Imprints, Inc. Technique for separating a mold from solidified imprinting material
US7670530B2 (en) 2006-01-20 2010-03-02 Molecular Imprints, Inc. Patterning substrates employing multiple chucks
JP4987012B2 (ja) 2005-12-08 2012-07-25 モレキュラー・インプリンツ・インコーポレーテッド 基板の両面パターニングする方法及びシステム
US8850980B2 (en) 2006-04-03 2014-10-07 Canon Nanotechnologies, Inc. Tessellated patterns in imprint lithography
US7802978B2 (en) 2006-04-03 2010-09-28 Molecular Imprints, Inc. Imprinting of partial fields at the edge of the wafer
US8142850B2 (en) 2006-04-03 2012-03-27 Molecular Imprints, Inc. Patterning a plurality of fields on a substrate to compensate for differing evaporation times
WO2007117524A2 (en) * 2006-04-03 2007-10-18 Molecular Imprints, Inc. Method of concurrently patterning a substrate having a plurality of fields and alignment marks
US7547398B2 (en) * 2006-04-18 2009-06-16 Molecular Imprints, Inc. Self-aligned process for fabricating imprint templates containing variously etched features
US8012395B2 (en) 2006-04-18 2011-09-06 Molecular Imprints, Inc. Template having alignment marks formed of contrast material
JP2008198916A (ja) * 2007-02-15 2008-08-28 Spansion Llc 半導体装置及びその製造方法
US7862737B2 (en) * 2007-08-10 2011-01-04 Tdk Corporation Planarizing method
JP2009145745A (ja) * 2007-12-17 2009-07-02 Hitachi Displays Ltd 液晶表示装置およびその製造方法
CN102592989B (zh) * 2011-01-07 2015-04-08 中国科学院微电子研究所 层间电介质的近界面平坦化回刻方法
US9097994B2 (en) * 2012-01-27 2015-08-04 Sematech, Inc. Abrasive-free planarization for EUV mask substrates
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
EP0049400B1 (de) * 1980-09-22 1984-07-11 Kabushiki Kaisha Toshiba Verfahren zum Glätten einer isolierenden Schicht auf einem Halbleiterkörper
US4358356A (en) * 1981-04-13 1982-11-09 Intel Magnetics, Inc. Method for sloping insulative layer in bubble memory
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
JPS59147433A (ja) * 1983-02-14 1984-08-23 Hitachi Ltd エツチング装置
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
JPS6113619A (ja) * 1984-06-29 1986-01-21 Agency Of Ind Science & Technol 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0243273A3 (en) 1989-11-08
DE3750169D1 (de) 1994-08-11
EP0243273B1 (de) 1994-07-06
EP0243273A2 (de) 1987-10-28
JPS6323337A (ja) 1988-01-30
US4676868A (en) 1987-06-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition