DE3751474T2 - Verzweigungsstrom-Koprozessor. - Google Patents

Verzweigungsstrom-Koprozessor.

Info

Publication number
DE3751474T2
DE3751474T2 DE3751474T DE3751474T DE3751474T2 DE 3751474 T2 DE3751474 T2 DE 3751474T2 DE 3751474 T DE3751474 T DE 3751474T DE 3751474 T DE3751474 T DE 3751474T DE 3751474 T2 DE3751474 T2 DE 3751474T2
Authority
DE
Germany
Prior art keywords
branch current
current coprocessor
coprocessor
branch
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751474T
Other languages
English (en)
Other versions
DE3751474D1 (de
Inventor
Philip George Emma
James Herbert Pomerene
Thomas Roberts Puzak
Rudolph Nathan Rechtschaffen
Frank John Sparacio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3751474D1 publication Critical patent/DE3751474D1/de
Publication of DE3751474T2 publication Critical patent/DE3751474T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
DE3751474T 1986-03-13 1987-02-05 Verzweigungsstrom-Koprozessor. Expired - Fee Related DE3751474T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/839,312 US4991080A (en) 1986-03-13 1986-03-13 Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions

Publications (2)

Publication Number Publication Date
DE3751474D1 DE3751474D1 (de) 1995-09-28
DE3751474T2 true DE3751474T2 (de) 1996-03-28

Family

ID=25279394

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751474T Expired - Fee Related DE3751474T2 (de) 1986-03-13 1987-02-05 Verzweigungsstrom-Koprozessor.

Country Status (5)

Country Link
US (1) US4991080A (de)
EP (1) EP0236745B1 (de)
JP (1) JPS62221036A (de)
CA (1) CA1268555A (de)
DE (1) DE3751474T2 (de)

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440704A (en) * 1986-08-26 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Data processor having branch predicting function
US5265220A (en) * 1986-12-23 1993-11-23 Nec Corporation Address control device for effectively controlling an address storing operation even when a request is subsequently cancelled
JP2723238B2 (ja) * 1988-01-18 1998-03-09 株式会社東芝 情報処理装置
IL92605A0 (en) * 1988-12-19 1990-08-31 Bull Hn Information Syst Production line method and apparatus for high performance instruction execution
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
EP0378415A3 (de) * 1989-01-13 1991-09-25 International Business Machines Corporation Verteilungsmechanismus für mehrere Befehle
DE69030931T2 (de) * 1989-04-24 1998-01-15 Ibm Mehrfachsequenzprozessorsystem
US6253307B1 (en) * 1989-05-04 2001-06-26 Texas Instruments Incorporated Data processing device with mask and status bits for selecting a set of status conditions
US5652910A (en) * 1989-05-04 1997-07-29 Texas Instruments Incorporated Devices and systems with conditional instructions
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
JP2570859B2 (ja) * 1989-05-25 1997-01-16 日本電気株式会社 データ処理装置
JP2680899B2 (ja) * 1989-08-28 1997-11-19 日本電気株式会社 情報処理装置及びその制御方法
JPH0650465B2 (ja) * 1989-10-16 1994-06-29 株式会社東芝 分岐制御回路
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
EP0442116A3 (en) * 1990-02-13 1993-03-03 Hewlett-Packard Company Pipeline method and apparatus
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5212794A (en) * 1990-06-01 1993-05-18 Hewlett-Packard Company Method for optimizing computer code to provide more efficient execution on computers having cache memories
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
US5276882A (en) * 1990-07-27 1994-01-04 International Business Machines Corp. Subroutine return through branch history table
US5530941A (en) * 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
US5276825A (en) * 1991-03-12 1994-01-04 Chips & Technologies, Inc. Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction
US5394530A (en) * 1991-03-15 1995-02-28 Nec Corporation Arrangement for predicting a branch target address in the second iteration of a short loop
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5265199A (en) * 1991-05-22 1993-11-23 Silicon Graphics, Inc. Method and apparatus for accomplishing Z-buffering by prediction
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
JPH0628184A (ja) * 1991-08-26 1994-02-04 Internatl Business Mach Corp <Ibm> ブランチ予測方法及びブランチプロセッサ
JP3182438B2 (ja) * 1991-10-28 2001-07-03 株式会社日立製作所 データプロセッサ
US5333283A (en) * 1991-10-29 1994-07-26 International Business Machines Corporation Case block table for predicting the outcome of blocks of conditional branches having a common operand
US5280592A (en) * 1992-01-03 1994-01-18 Amdahl Corporation Domain interlock
CA2124333A1 (en) * 1992-02-27 1993-09-02 John A. Saba Cpu having pipelined instruction unit and effective address calculation unit with retained virtual address capability
US5434985A (en) * 1992-08-11 1995-07-18 International Business Machines Corporation Simultaneous prediction of multiple branches for superscalar processing
US5442767A (en) * 1992-10-23 1995-08-15 International Business Machines Corporation Address prediction to avoid address generation interlocks in computer systems
US5696958A (en) * 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
US5590368A (en) * 1993-03-31 1996-12-31 Intel Corporation Method and apparatus for dynamically expanding the pipeline of a microprocessor
EP0623874A1 (de) * 1993-05-03 1994-11-09 International Business Machines Corporation Verfahren zur Ausführung von Befehlen in einer Schleife
JPH09500989A (ja) * 1993-05-14 1997-01-28 インテル・コーポレーション 分岐ターゲット・バッファにおける推論履歴
JP2596712B2 (ja) * 1993-07-01 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 近接した分岐命令を含む命令の実行を管理するシステム及び方法
DK0661625T3 (da) * 1994-01-03 2000-04-03 Intel Corp Fremgangsmåde og apparatur til implementering af et firetrins system til bestemmelse af programforgreninger (Four Stage Bra
US5644779A (en) * 1994-04-15 1997-07-01 International Business Machines Corporation Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction
US5566317A (en) * 1994-06-14 1996-10-15 International Business Machines Corporation Method and apparatus for computer disk drive management
JP3599409B2 (ja) * 1994-06-14 2004-12-08 株式会社ルネサステクノロジ 分岐予測装置
US5664135A (en) * 1994-09-28 1997-09-02 Hewlett-Packard Company Apparatus and method for reducing delays due to branches
US5675758A (en) * 1994-11-15 1997-10-07 Advanced Micro Devices, Inc. Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5850542A (en) * 1995-09-15 1998-12-15 International Business Machines Corporation Microprocessor instruction hedge-fetching in a multiprediction branch environment
US5815700A (en) * 1995-12-22 1998-09-29 Intel Corporation Branch prediction table having pointers identifying other branches within common instruction cache lines
JP3510729B2 (ja) * 1996-02-29 2004-03-29 三洋電機株式会社 命令実行方法および命令実行装置
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5918044A (en) * 1996-10-31 1999-06-29 International Business Machines Corporation Apparatus and method for instruction fetching using a multi-port instruction cache directory
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5961631A (en) * 1997-07-16 1999-10-05 Arm Limited Data processing apparatus and method for pre-fetching an instruction in to an instruction cache
US6157988A (en) 1997-08-01 2000-12-05 Micron Technology, Inc. Method and apparatus for high performance branching in pipelined microsystems
US5934212A (en) * 1997-09-04 1999-08-10 Gitlin; Harris M Two part sewing system for large work pieces
US6012138A (en) * 1997-12-19 2000-01-04 Lsi Logic Corporation Dynamically variable length CPU pipeline for efficiently executing two instruction sets
US6314493B1 (en) * 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
US6026488A (en) * 1998-02-20 2000-02-15 International Business Machines Corporation Method for conditional hedge fetching into cache storage
US6035392A (en) * 1998-02-20 2000-03-07 International Business Machines Corporation Computer with optimizing hardware for conditional hedge fetching into cache storage
JP3741870B2 (ja) * 1998-08-07 2006-02-01 富士通株式会社 命令及びデータの先読み方法、マイクロコントローラ、疑似命令検出回路
US6430682B1 (en) * 1998-09-11 2002-08-06 Agere Systems Guardian Corp. Reliable branch predictions for real-time applications
JP2000132390A (ja) * 1998-10-23 2000-05-12 Toshiba Corp プロセッサ及び分岐予測器
US6205544B1 (en) * 1998-12-21 2001-03-20 Intel Corporation Decomposition of instructions into branch and sequential code sections
US6912650B2 (en) * 2000-03-21 2005-06-28 Fujitsu Limited Pre-prefetching target of following branch instruction based on past history
JP3981238B2 (ja) * 1999-12-27 2007-09-26 富士通株式会社 情報処理装置
US6415356B1 (en) * 2000-01-14 2002-07-02 Sun Microsystems, Inc. Method and apparatus for using an assist processor to pre-fetch data values for a primary processor
US6728872B1 (en) * 2000-02-04 2004-04-27 International Business Machines Corporation Method and apparatus for verifying that instructions are pipelined in correct architectural sequence
US6772321B2 (en) 2000-05-04 2004-08-03 Sun Microsystems, Inc. Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor
US20030188141A1 (en) * 2002-03-29 2003-10-02 Shailender Chaudhry Time-multiplexed speculative multi-threading to support single-threaded applications
US6553362B2 (en) * 2000-07-14 2003-04-22 Hewlett-Packard Development Company, L.P. Case-reduced verification condition generation system and method using weakest precondition operator expressed using strongest postcondition operators
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US6681318B2 (en) 2000-09-08 2004-01-20 Sun Microsystems, Inc. Method and apparatus for using an assist processor to prefetch instructions for a primary processor
US6671794B1 (en) 2000-10-02 2003-12-30 International Business Machines Corporation Address generation interlock detection
US7337306B2 (en) * 2000-12-29 2008-02-26 Stmicroelectronics, Inc. Executing conditional branch instructions in a data processor having a clustered architecture
US7287147B1 (en) 2000-12-29 2007-10-23 Mips Technologies, Inc. Configurable co-processor interface
US7237090B1 (en) 2000-12-29 2007-06-26 Mips Technologies, Inc. Configurable out-of-order data transfer in a coprocessor interface
JP2004519796A (ja) * 2001-04-11 2004-07-02 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 分岐構造を持つエミュレーションコプロセッサ
US6950929B2 (en) * 2001-05-24 2005-09-27 Samsung Electronics Co., Ltd. Loop instruction processing using loop buffer in a data processing device having a coprocessor
JP4020692B2 (ja) * 2002-05-08 2007-12-12 三菱電機株式会社 針送りミシン
US20040193855A1 (en) * 2003-03-31 2004-09-30 Nicolas Kacevas System and method for branch prediction access
US7502725B2 (en) * 2004-04-29 2009-03-10 International Business Machines Corporation Method, system and computer program product for register management in a simulation environment
JP2006048132A (ja) * 2004-07-30 2006-02-16 Fujitsu Ltd 分岐予測装置、分岐予測装置の制御方法、情報処理装置
JP5444889B2 (ja) * 2009-06-30 2014-03-19 富士通株式会社 演算処理装置および演算処理装置の制御方法
US10180841B2 (en) 2014-12-22 2019-01-15 Centipede Semi Ltd. Early termination of segment monitoring in run-time code parallelization
US10296346B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences based on pre-monitoring
US10296350B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences
US20180129500A1 (en) * 2016-11-06 2018-05-10 Centipede Semi Ltd. Single-thread processing of multiple code regions
US20190369999A1 (en) * 2018-06-04 2019-12-05 Advanced Micro Devices, Inc. Storing incidental branch predictions to reduce latency of misprediction recovery
US11106466B2 (en) * 2018-06-18 2021-08-31 International Business Machines Corporation Decoupling of conditional branches
US20230315476A1 (en) * 2022-03-30 2023-10-05 Huawei Technologies Co., Ltd. Systems and methods for load-dependent-branch pre-resolution

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3559183A (en) * 1968-02-29 1971-01-26 Ibm Instruction sequence control
US3707725A (en) * 1970-06-19 1972-12-26 Ibm Program execution tracing system improvements
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
US4155120A (en) * 1977-12-01 1979-05-15 Burroughs Corporation Apparatus and method for controlling microinstruction sequencing by selectively inhibiting microinstruction execution
US4270167A (en) * 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system
US4338675A (en) * 1980-02-13 1982-07-06 Intel Corporation Numeric data processor
JPS5927935B2 (ja) * 1980-02-29 1984-07-09 株式会社日立製作所 情報処理装置
JPS56149646A (en) * 1980-04-21 1981-11-19 Toshiba Corp Operation controller
US4442484A (en) * 1980-10-14 1984-04-10 Intel Corporation Microprocessor memory management and protection mechanism
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
US4521851A (en) * 1982-10-13 1985-06-04 Honeywell Information Systems Inc. Central processor
US4597041A (en) * 1982-11-15 1986-06-24 Data General Corp. Method and apparatus for enhancing the operation of a data processing system
US4569018A (en) * 1982-11-15 1986-02-04 Data General Corp. Digital data processing system having dual-purpose scratchpad and address translation memory
US4819154A (en) * 1982-12-09 1989-04-04 Sequoia Systems, Inc. Memory back up system with one cache memory and two physically separated main memories
JPS6027945A (ja) * 1983-07-27 1985-02-13 Nec Corp 命令取出装置
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
US4710866A (en) * 1983-09-12 1987-12-01 Motorola, Inc. Method and apparatus for validating prefetched instruction
US4608659A (en) * 1983-09-30 1986-08-26 Honeywell Information Systems Inc. Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands
US4594651A (en) * 1984-01-18 1986-06-10 General Electric Company Concurrent processor for control
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US4691277A (en) * 1984-10-24 1987-09-01 International Business Machines Corp. Small instruction cache using branch target table to effect instruction prefetch
JPH0789319B2 (ja) * 1985-04-22 1995-09-27 株式会社日立製作所 デ−タ処理装置における先行制御装置
US4701842A (en) * 1985-10-04 1987-10-20 International Business Machines Corporation Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
EP0229619B1 (de) * 1986-01-07 1997-08-06 Nec Corporation Befehlsvorabrufgerät mit einer Schaltung zum Prüfen der Vorhersage eines Verzweigungsbefehls vor seiner Ausführung
US4821183A (en) * 1986-12-04 1989-04-11 International Business Machines Corporation A microsequencer circuit with plural microprogrom instruction counters
JP2603626B2 (ja) * 1987-01-16 1997-04-23 三菱電機株式会社 データ処理装置

Also Published As

Publication number Publication date
US4991080A (en) 1991-02-05
CA1268555A (en) 1990-05-01
EP0236745A2 (de) 1987-09-16
DE3751474D1 (de) 1995-09-28
EP0236745B1 (de) 1995-08-23
JPS62221036A (ja) 1987-09-29
EP0236745A3 (de) 1991-12-04

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