DE3751503D1 - Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen. - Google Patents

Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.

Info

Publication number
DE3751503D1
DE3751503D1 DE3751503T DE3751503T DE3751503D1 DE 3751503 D1 DE3751503 D1 DE 3751503D1 DE 3751503 T DE3751503 T DE 3751503T DE 3751503 T DE3751503 T DE 3751503T DE 3751503 D1 DE3751503 D1 DE 3751503D1
Authority
DE
Germany
Prior art keywords
decode
ability
parallel
data processor
pipeline structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751503T
Other languages
English (en)
Other versions
DE3751503T2 (de
Inventor
Kazunori Hitachi Dai- Kuriyama
Yooichi Hitachi Tenno Shintani
Akira Hitachi Koyasuda Yamaoka
Tohru Shonai
Eiki Hitachi Koyasudai Kamada
Kiyoshi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3751503D1 publication Critical patent/DE3751503D1/de
Application granted granted Critical
Publication of DE3751503T2 publication Critical patent/DE3751503T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3816Instruction alignment, e.g. cache line crossing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/3822Parallel decoding, e.g. parallel decode units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
DE3751503T 1986-03-26 1987-03-24 Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen. Expired - Fee Related DE3751503T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6565186 1986-03-26

Publications (2)

Publication Number Publication Date
DE3751503D1 true DE3751503D1 (de) 1995-10-12
DE3751503T2 DE3751503T2 (de) 1996-05-09

Family

ID=13293121

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751503T Expired - Fee Related DE3751503T2 (de) 1986-03-26 1987-03-24 Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.

Country Status (4)

Country Link
US (1) US4858105A (de)
EP (1) EP0239081B1 (de)
JP (1) JP2559399B2 (de)
DE (1) DE3751503T2 (de)

Families Citing this family (250)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
JP2902402B2 (ja) * 1987-09-30 1999-06-07 三菱電機株式会社 データ処理装置
JPH0766324B2 (ja) * 1988-03-18 1995-07-19 三菱電機株式会社 データ処理装置
US5202967A (en) * 1988-08-09 1993-04-13 Matsushita Electric Industrial Co., Ltd. Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
DE68926701T2 (de) * 1988-08-09 1997-02-20 Matsushita Electric Ind Co Ltd Datenverarbeitungsgerät zur parallelen Dekodierung und parallelen Ausführung von Befehlen mit variabler Wortlänge
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
JP2810068B2 (ja) 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
JP2504156B2 (ja) * 1989-01-25 1996-06-05 日本電気株式会社 情報処理装置
US5148528A (en) * 1989-02-03 1992-09-15 Digital Equipment Corporation Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length
KR0163179B1 (ko) * 1989-03-31 1999-01-15 미다 가쓰시게 데이타 프로세서
US5179691A (en) * 1989-04-12 1993-01-12 Unisys Corporation N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M
US5617574A (en) * 1989-05-04 1997-04-01 Texas Instruments Incorporated Devices, systems and methods for conditional instructions
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
US5353418A (en) * 1989-05-26 1994-10-04 Massachusetts Institute Of Technology System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread
WO1990014629A2 (en) * 1989-05-26 1990-11-29 Massachusetts Institute Of Technology Parallel multithreaded data processing system
JPH0328911A (ja) * 1989-06-26 1991-02-07 Mitsubishi Electric Corp マイクロプロセッサ
DE69032812T2 (de) * 1989-07-07 1999-04-29 Hitachi Ltd Vorrichtung und Verfahren zur parallelen Verarbeitung
JP2710994B2 (ja) * 1989-08-29 1998-02-10 三菱電機株式会社 データ処理装置
US5745723A (en) * 1989-09-04 1998-04-28 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
JPH07120284B2 (ja) * 1989-09-04 1995-12-20 三菱電機株式会社 データ処理装置
US5615349A (en) * 1990-09-04 1997-03-25 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
JP2816248B2 (ja) * 1989-11-08 1998-10-27 株式会社日立製作所 データプロセッサ
JP2507638B2 (ja) * 1989-12-01 1996-06-12 三菱電機株式会社 デ―タ処理装置
US5226131A (en) * 1989-12-27 1993-07-06 The United States Of America As Represented By The United States Department Of Energy Sequencing and fan-out mechanism for causing a set of at least two sequential instructions to be performed in a dataflow processing computer
JP2818249B2 (ja) * 1990-03-30 1998-10-30 株式会社東芝 電子計算機
CA2037708C (en) * 1990-05-04 1998-01-20 Richard J. Eickemeyer General purpose compound apparatus for instruction-level parallel processors
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
WO1991017496A1 (en) * 1990-05-04 1991-11-14 International Business Machines Corporation System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction
ATE146611T1 (de) * 1990-05-04 1997-01-15 Ibm Maschinenarchitektur für skalaren verbundbefehlssatz
US5197135A (en) * 1990-06-26 1993-03-23 International Business Machines Corporation Memory management for scalable compound instruction set machines with in-memory compounding
JPH0778737B2 (ja) * 1990-05-10 1995-08-23 インターナショナル・ビジネス・マシーンズ・コーポレイション キャッシュに対する複合化プリプロセッサ方式
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
CA2045705A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites In-register data manipulation in reduced instruction set processor
JP2834292B2 (ja) * 1990-08-15 1998-12-09 株式会社日立製作所 データ・プロセッサ
US5163139A (en) * 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
US5655096A (en) * 1990-10-12 1997-08-05 Branigin; Michael H. Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution
JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
JP2682232B2 (ja) * 1990-11-21 1997-11-26 松下電器産業株式会社 浮動小数点演算処理装置
JP2911278B2 (ja) * 1990-11-30 1999-06-23 松下電器産業株式会社 プロセッサ
US5261063A (en) * 1990-12-07 1993-11-09 Ibm Corp. Pipeline apparatus having pipeline mode eecuting instructions from plural programs and parallel mode executing instructions from one of the plural programs
EP0498067A2 (de) * 1991-02-08 1992-08-12 International Business Machines Corporation Mikrokodeerzeugung für eine Maschine mit skalierbarem Verbundbefehlssatz
US5488729A (en) * 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
JP3105197B2 (ja) 1991-06-24 2000-10-30 株式会社日立製作所 除算回路及び除算方法
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JP2779557B2 (ja) * 1991-07-09 1998-07-23 三菱電機株式会社 並列演算処理装置
JP2875909B2 (ja) * 1991-07-12 1999-03-31 三菱電機株式会社 並列演算処理装置
US5430850A (en) * 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
US5283874A (en) * 1991-10-21 1994-02-01 Intel Corporation Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even if they begin to process at the same microprocessor of the issue fee
JP3369204B2 (ja) * 1991-10-25 2003-01-20 株式会社東芝 プログラマブルコントローラ
EP0544083A3 (en) * 1991-11-26 1994-09-14 Ibm Interleaved risc-type parallel processor and processing methods
GB2263565B (en) * 1992-01-23 1995-08-30 Intel Corp Microprocessor with apparatus for parallel execution of instructions
SG45251A1 (en) * 1992-02-06 1998-01-16 Intel Corp Rotators in machine instruction length calculation
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
DE69308548T2 (de) 1992-05-01 1997-06-12 Seiko Epson Corp Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
US5416913A (en) * 1992-07-27 1995-05-16 Intel Corporation Method and apparatus for dependency checking in a multi-pipelined microprocessor
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
DE69329778T2 (de) * 1992-09-29 2001-04-26 Seiko Epson Corp System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
EP0682789B1 (de) 1992-12-31 1998-09-09 Seiko Epson Corporation System und verfahren zur änderung der namen von registern
EP0625746A1 (de) * 1993-05-19 1994-11-23 Siemens Nixdorf Informationssysteme Aktiengesellschaft Befehlsaufbereitungseinheit für Verarbeitungsprozessoren in Datenverarbeitungsanlagen
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
DE69434669T2 (de) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
DE69427265T2 (de) 1993-10-29 2002-05-02 Advanced Micro Devices Inc Superskalarbefehlsdekoder
US5590351A (en) * 1994-01-21 1996-12-31 Advanced Micro Devices, Inc. Superscalar execution unit for sequential instruction pointer updates and segment limit checks
US5418736A (en) * 1994-03-11 1995-05-23 Nexgen, Inc. Optimized binary adders and comparators for inputs having different widths
EP0685794A1 (de) * 1994-06-01 1995-12-06 Advanced Micro Devices, Inc. System zum Erzeugen von Fliesskomma-Prüfvektoren
US5696955A (en) * 1994-06-01 1997-12-09 Advanced Micro Devices, Inc. Floating point stack and exchange instruction
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5832249A (en) * 1995-01-25 1998-11-03 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5878244A (en) * 1995-01-25 1999-03-02 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US5819057A (en) * 1995-01-25 1998-10-06 Advanced Micro Devices, Inc. Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units
US6006324A (en) 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5758114A (en) * 1995-04-12 1998-05-26 Advanced Micro Devices, Inc. High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5887152A (en) * 1995-04-12 1999-03-23 Advanced Micro Devices, Inc. Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
US5819059A (en) * 1995-04-12 1998-10-06 Advanced Micro Devices, Inc. Predecode unit adapted for variable byte-length instruction set processors and method of operating the same
US5991869A (en) * 1995-04-12 1999-11-23 Advanced Micro Devices, Inc. Superscalar microprocessor including a high speed instruction alignment unit
US5835753A (en) * 1995-04-12 1998-11-10 Advanced Micro Devices, Inc. Microprocessor with dynamically extendable pipeline stages and a classifying circuit
US5832297A (en) * 1995-04-12 1998-11-03 Advanced Micro Devices, Inc. Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
US5802588A (en) * 1995-04-12 1998-09-01 Advanced Micro Devices, Inc. Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer
US5822574A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same
US5900012A (en) * 1995-05-10 1999-05-04 Advanced Micro Devices, Inc. Storage device having varying access times and a superscalar microprocessor employing the same
US5875315A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Parallel and scalable instruction scanning unit
US5768610A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Lookahead register value generator and a superscalar microprocessor employing same
US5859991A (en) * 1995-06-07 1999-01-12 Advanced Micro Devices, Inc. Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
US5768574A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5680578A (en) * 1995-06-07 1997-10-21 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify expanded functionality and a computer system employing same
US5878255A (en) * 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US6604190B1 (en) 1995-06-07 2003-08-05 Advanced Micro Devices, Inc. Data address prediction structure and a method for operating the same
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5854921A (en) * 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US5826071A (en) * 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
US5987561A (en) * 1995-08-31 1999-11-16 Advanced Micro Devices, Inc. Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5752069A (en) * 1995-08-31 1998-05-12 Advanced Micro Devices, Inc. Superscalar microprocessor employing away prediction structure
US5860104A (en) * 1995-08-31 1999-01-12 Advanced Micro Devices, Inc. Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates
US5845323A (en) * 1995-08-31 1998-12-01 Advanced Micro Devices, Inc. Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time
US5893146A (en) * 1995-08-31 1999-04-06 Advanced Micro Design, Inc. Cache structure having a reduced tag comparison to enable data transfer from said cache
US5745724A (en) * 1996-01-26 1998-04-28 Advanced Micro Devices, Inc. Scan chain for rapidly identifying first or second objects of selected types in a sequential list
US5872947A (en) * 1995-10-24 1999-02-16 Advanced Micro Devices, Inc. Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions
US5933618A (en) * 1995-10-30 1999-08-03 Advanced Micro Devices, Inc. Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5892936A (en) * 1995-10-30 1999-04-06 Advanced Micro Devices, Inc. Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5787474A (en) * 1995-11-20 1998-07-28 Advanced Micro Devices, Inc. Dependency checking structure for a pair of caches which are accessed from different pipeline stages of an instruction processing pipeline
US5903910A (en) * 1995-11-20 1999-05-11 Advanced Micro Devices, Inc. Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline
US5835744A (en) * 1995-11-20 1998-11-10 Advanced Micro Devices, Inc. Microprocessor configured to swap operands in order to minimize dependency checking logic
US5765035A (en) * 1995-11-20 1998-06-09 Advanced Micro Devices, Inc. Recorder buffer capable of detecting dependencies between accesses to a pair of caches
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5822559A (en) * 1996-01-02 1998-10-13 Advanced Micro Devices, Inc. Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions
US5819080A (en) * 1996-01-02 1998-10-06 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor
US5742791A (en) 1996-02-14 1998-04-21 Advanced Micro Devices, Inc. Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor
US5848287A (en) 1996-02-20 1998-12-08 Advanced Micro Devices, Inc. Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches
US5787266A (en) * 1996-02-20 1998-07-28 Advanced Micro Devices, Inc. Apparatus and method for accessing special registers without serialization
US5687110A (en) * 1996-02-20 1997-11-11 Advanced Micro Devices, Inc. Array having an update circuit for updating a storage location with a value stored in another storage location
US5961580A (en) * 1996-02-20 1999-10-05 Advanced Micro Devices, Inc. Apparatus and method for efficiently calculating a linear address in a microprocessor
US5790821A (en) * 1996-03-08 1998-08-04 Advanced Micro Devices, Inc. Control bit vector storage for storing control vectors corresponding to instruction operations in a microprocessor
US5813033A (en) * 1996-03-08 1998-09-22 Advanced Micro Devices, Inc. Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache
US5758187A (en) * 1996-03-15 1998-05-26 Adaptec, Inc. Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure
US5892969A (en) * 1996-03-15 1999-04-06 Adaptec, Inc. Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation
US5768621A (en) * 1996-03-15 1998-06-16 Adaptec, Inc. Chain manager for use in executing a chain of I/O command blocks
US5797034A (en) * 1996-03-15 1998-08-18 Adaptec, Inc. Method for specifying execution of only one of a pair of I/O command blocks in a chain structure
US5812877A (en) * 1996-03-15 1998-09-22 Adaptec, Inc. I/O command block chain structure in a memory
US5923896A (en) * 1996-03-15 1999-07-13 Adaptec, Inc. Method for sequencing execution of I/O command blocks in a chain structure by setting hold-off flags and configuring a counter in each I/O command block
US5850567A (en) * 1996-03-15 1998-12-15 Adaptec, Inc. Method for specifying concurrent execution of a string of I/O command blocks in a chain structure
US5838943A (en) 1996-03-26 1998-11-17 Advanced Micro Devices, Inc. Apparatus for speculatively storing and restoring data to a cache memory
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
US6085302A (en) * 1996-04-17 2000-07-04 Advanced Micro Devices, Inc. Microprocessor having address generation units for efficient generation of memory operation addresses
US5835968A (en) * 1996-04-17 1998-11-10 Advanced Micro Devices, Inc. Apparatus for providing memory and register operands concurrently to functional units
SE509499C2 (sv) 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur
US5796997A (en) * 1996-05-15 1998-08-18 Hewlett-Packard Company Fast nullify system and method for transforming a nullify function into a select function
US6108769A (en) 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5748978A (en) * 1996-05-17 1998-05-05 Advanced Micro Devices, Inc. Byte queue divided into multiple subqueues for optimizing instruction selection logic
US5918056A (en) * 1996-05-17 1999-06-29 Advanced Micro Devices, Inc. Segmentation suspend mode for real-time interrupt support
US5835511A (en) * 1996-05-17 1998-11-10 Advanced Micro Devices, Inc. Method and mechanism for checking integrity of byte enable signals
US5822560A (en) * 1996-05-23 1998-10-13 Advanced Micro Devices, Inc. Apparatus for efficient instruction execution via variable issue and variable control vectors per issue
US5813045A (en) * 1996-07-24 1998-09-22 Advanced Micro Devices, Inc. Conditional early data address generation mechanism for a microprocessor
US5903740A (en) * 1996-07-24 1999-05-11 Advanced Micro Devices, Inc. Apparatus and method for retiring instructions in excess of the number of accessible write ports
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US5867680A (en) * 1996-07-24 1999-02-02 Advanced Micro Devices, Inc. Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
US5946468A (en) * 1996-07-26 1999-08-31 Advanced Micro Devices, Inc. Reorder buffer having an improved future file for storing speculative instruction execution results
US5872943A (en) * 1996-07-26 1999-02-16 Advanced Micro Devices, Inc. Apparatus for aligning instructions using predecoded shift amounts
US5900013A (en) * 1996-07-26 1999-05-04 Advanced Micro Devices, Inc. Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries
US5915110A (en) * 1996-07-26 1999-06-22 Advanced Micro Devices, Inc. Branch misprediction recovery in a reorder buffer having a future file
US5872951A (en) * 1996-07-26 1999-02-16 Advanced Micro Design, Inc. Reorder buffer having a future file for storing speculative instruction execution results
US5765016A (en) * 1996-09-12 1998-06-09 Advanced Micro Devices, Inc. Reorder buffer configured to store both speculative and committed register states
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5870579A (en) * 1996-11-18 1999-02-09 Advanced Micro Devices, Inc. Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception
US5920710A (en) * 1996-11-18 1999-07-06 Advanced Micro Devices, Inc. Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
US5995749A (en) * 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US5954816A (en) * 1996-11-19 1999-09-21 Advanced Micro Devices, Inc. Branch selector prediction
US5978906A (en) * 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US6175906B1 (en) 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
US5881305A (en) * 1996-12-13 1999-03-09 Advanced Micro Devices, Inc. Register rename stack for a microprocessor
US5870580A (en) * 1996-12-13 1999-02-09 Advanced Micro Devices, Inc. Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies
US5983321A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
US5768555A (en) 1997-02-20 1998-06-16 Advanced Micro Devices, Inc. Reorder buffer employing last in buffer and last in line bits
US6141740A (en) * 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US6233672B1 (en) 1997-03-06 2001-05-15 Advanced Micro Devices, Inc. Piping rounding mode bits with floating point instructions to eliminate serialization
US5852727A (en) * 1997-03-10 1998-12-22 Advanced Micro Devices, Inc. Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
US5850532A (en) * 1997-03-10 1998-12-15 Advanced Micro Devices, Inc. Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched
US5968163A (en) 1997-03-10 1999-10-19 Advanced Micro Devices, Inc. Microcode scan unit for scanning microcode instructions using predecode data
US5859992A (en) * 1997-03-12 1999-01-12 Advanced Micro Devices, Inc. Instruction alignment using a dispatch list and a latch list
US5859998A (en) * 1997-03-19 1999-01-12 Advanced Micro Devices, Inc. Hierarchical microcode implementation of floating point instructions for a microprocessor
US5828873A (en) * 1997-03-19 1998-10-27 Advanced Micro Devices, Inc. Assembly queue for a floating point unit
US5930492A (en) * 1997-03-19 1999-07-27 Advanced Micro Devices, Inc. Rapid pipeline control using a control word and a steering word
US5887185A (en) * 1997-03-19 1999-03-23 Advanced Micro Devices, Inc. Interface for coupling a floating point unit to a reorder buffer
US5987235A (en) * 1997-04-04 1999-11-16 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
US5901076A (en) * 1997-04-16 1999-05-04 Advanced Micro Designs, Inc. Ripple carry shifter in a floating point arithmetic unit of a microprocessor
US6003128A (en) * 1997-05-01 1999-12-14 Advanced Micro Devices, Inc. Number of pipeline stages and loop length related counter differential based end-loop prediction
US6122729A (en) 1997-05-13 2000-09-19 Advanced Micro Devices, Inc. Prefetch buffer which stores a pointer indicating an initial predecode position
US5845101A (en) * 1997-05-13 1998-12-01 Advanced Micro Devices, Inc. Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US5940602A (en) * 1997-06-11 1999-08-17 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
US6009511A (en) * 1997-06-11 1999-12-28 Advanced Micro Devices, Inc. Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers
US5898865A (en) * 1997-06-12 1999-04-27 Advanced Micro Devices, Inc. Apparatus and method for predicting an end of loop for string instructions
US5983337A (en) * 1997-06-12 1999-11-09 Advanced Micro Devices, Inc. Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
US5933626A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for tracing microprocessor instructions
US5933629A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for detecting microbranches early
US6012125A (en) * 1997-06-20 2000-01-04 Advanced Micro Devices, Inc. Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
US5978901A (en) * 1997-08-21 1999-11-02 Advanced Micro Devices, Inc. Floating point and multimedia unit with data type reclassification capability
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US5931943A (en) * 1997-10-21 1999-08-03 Advanced Micro Devices, Inc. Floating point NaN comparison
US6032252A (en) * 1997-10-28 2000-02-29 Advanced Micro Devices, Inc. Apparatus and method for efficient loop control in a superscalar microprocessor
US5974542A (en) * 1997-10-30 1999-10-26 Advanced Micro Devices, Inc. Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6199154B1 (en) 1997-11-17 2001-03-06 Advanced Micro Devices, Inc. Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
US6154818A (en) * 1997-11-20 2000-11-28 Advanced Micro Devices, Inc. System and method of controlling access to privilege partitioned address space for a model specific register file
US6516395B1 (en) 1997-11-20 2003-02-04 Advanced Micro Devices, Inc. System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes
US6079003A (en) 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
US6079005A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
US5974432A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. On-the-fly one-hot encoding of leading zero count
US5870578A (en) * 1997-12-09 1999-02-09 Advanced Micro Devices, Inc. Workload balancing in a microprocessor for reduced instruction dispatch stalling
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6016545A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6112018A (en) 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Apparatus for exchanging two stack registers
US6018798A (en) * 1997-12-18 2000-01-25 Advanced Micro Devices, Inc. Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle
US6112296A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Floating point stack manipulation using a register map and speculative top of stack values
US6324639B1 (en) * 1998-03-30 2001-11-27 Matsushita Electric Industrial Co., Ltd. Instruction converting apparatus using parallel execution code
US6304954B1 (en) * 1998-04-20 2001-10-16 Rise Technology Company Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline
US6175908B1 (en) 1998-04-30 2001-01-16 Advanced Micro Devices, Inc. Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
US6141745A (en) * 1998-04-30 2000-10-31 Advanced Micro Devices, Inc. Functional bit identifying a prefix byte via a particular state regardless of type of instruction
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6230262B1 (en) 1998-07-31 2001-05-08 Advanced Micro Devices, Inc. Processor configured to selectively free physical registers upon retirement of instructions
US6742110B2 (en) 1998-10-06 2004-05-25 Texas Instruments Incorporated Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution
EP0992893B1 (de) 1998-10-06 2008-12-31 Texas Instruments Inc. Überprüfung von Befehlsparallelismus
US6330657B1 (en) * 1999-05-18 2001-12-11 Ip-First, L.L.C. Pairing of micro instructions in the instruction queue
US6438664B1 (en) 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Microcode patch device and method for patching microcode using match registers and patch routines
US6442707B1 (en) 1999-10-29 2002-08-27 Advanced Micro Devices, Inc. Alternate fault handler
US7418580B1 (en) * 1999-12-02 2008-08-26 International Business Machines Corporation Dynamic object-level code transaction for improved performance of a computer
US6848024B1 (en) 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6732234B1 (en) * 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6877084B1 (en) 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
US6981132B2 (en) 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US7366876B1 (en) * 2000-10-31 2008-04-29 Analog Devices, Inc. Efficient emulation instruction dispatch based on instruction width
US6738792B1 (en) 2001-03-09 2004-05-18 Advanced Micro Devices, Inc. Parallel mask generator
US7711926B2 (en) 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US6826681B2 (en) 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7051190B2 (en) * 2002-06-25 2006-05-23 Intel Corporation Intra-instruction fusion
US7398372B2 (en) * 2002-06-25 2008-07-08 Intel Corporation Fusing load and alu operations
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20100037020A1 (en) * 2008-08-07 2010-02-11 Seagate Technology Llc Pipelined memory access method and architecture therefore
EP2539808A4 (de) * 2010-02-22 2015-10-14 Analog Devices Inc Superskalare steuerung für einen wahrscheinlichkeitsberechner
US10311191B2 (en) 2017-01-26 2019-06-04 Advanced Micro Devices, Inc. Memory including side-car arrays with irregular sized entries

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771138A (en) * 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
JPS5744173B2 (de) * 1975-02-27 1982-09-20
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
JPS5729152A (en) * 1980-07-28 1982-02-17 Fujitsu Ltd Information processor prefetching instruction
US4430706A (en) * 1980-10-27 1984-02-07 Burroughs Corporation Branch prediction apparatus and method for a data processing system
JPS57137944A (en) * 1981-02-20 1982-08-25 Fujitsu Ltd General register advance control system
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4532589A (en) * 1981-12-02 1985-07-30 Hitachi, Ltd. Digital data processor with two operation units
JPS58151655A (ja) * 1982-03-03 1983-09-08 Fujitsu Ltd 情報処理装置
JPS58189738A (ja) * 1982-04-30 1983-11-05 Hitachi Ltd デ−タ処理システム
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4594659A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Method and apparatus for prefetching instructions for a central execution pipeline unit
US4613935A (en) * 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4635188A (en) * 1983-07-29 1987-01-06 Hewlett-Packard Company Means for fast instruction decoding for a computer
US4685058A (en) * 1983-08-29 1987-08-04 Amdahl Corporation Two-stage pipelined execution unit and control stores
JPS60140435A (ja) * 1983-12-28 1985-07-25 Hitachi Ltd 命令処理装置
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
US4775927A (en) * 1984-10-31 1988-10-04 International Business Machines Corporation Processor including fetch operation for branch instruction with control tag
JPH0769818B2 (ja) * 1984-10-31 1995-07-31 株式会社日立製作所 デ−タ処理装置
US4794517A (en) * 1985-04-15 1988-12-27 International Business Machines Corporation Three phased pipelined signal processor

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