DE3751920D1 - Isolationsverfahren für integrierte Schaltungen - Google Patents

Isolationsverfahren für integrierte Schaltungen

Info

Publication number
DE3751920D1
DE3751920D1 DE3751920T DE3751920T DE3751920D1 DE 3751920 D1 DE3751920 D1 DE 3751920D1 DE 3751920 T DE3751920 T DE 3751920T DE 3751920 T DE3751920 T DE 3751920T DE 3751920 D1 DE3751920 D1 DE 3751920D1
Authority
DE
Germany
Prior art keywords
integrated circuits
isolation process
isolation
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3751920T
Other languages
English (en)
Other versions
DE3751920T2 (de
Inventor
Richard A Chapman
Clarence Wan-Hsn Teng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE3751920D1 publication Critical patent/DE3751920D1/de
Application granted granted Critical
Publication of DE3751920T2 publication Critical patent/DE3751920T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
DE3751920T 1986-07-07 1987-07-03 Isolationsverfahren für integrierte Schaltungen Expired - Lifetime DE3751920T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/882,732 US4842675A (en) 1986-07-07 1986-07-07 Integrated circuit isolation process

Publications (2)

Publication Number Publication Date
DE3751920D1 true DE3751920D1 (de) 1996-11-14
DE3751920T2 DE3751920T2 (de) 1997-02-13

Family

ID=25381230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751920T Expired - Lifetime DE3751920T2 (de) 1986-07-07 1987-07-03 Isolationsverfahren für integrierte Schaltungen

Country Status (6)

Country Link
US (1) US4842675A (de)
EP (1) EP0252450B1 (de)
JP (1) JPS6340337A (de)
KR (1) KR960016502B1 (de)
CN (1) CN1013160B (de)
DE (1) DE3751920T2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847672A (en) * 1988-02-29 1989-07-11 Fairchild Semiconductor Corporation Integrated circuit die with resistive substrate isolation of multiple circuits
US4942449A (en) * 1988-03-28 1990-07-17 General Electric Company Fabrication method and structure for field isolation in field effect transistors on integrated circuit chips
IT1236994B (it) * 1989-12-29 1993-05-12 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi semiconduttori mos di potenza e dispositivi con esso ottenuti
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5192706A (en) * 1990-08-30 1993-03-09 Texas Instruments Incorporated Method for semiconductor isolation
US5130268A (en) * 1991-04-05 1992-07-14 Sgs-Thomson Microelectronics, Inc. Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby
US5310692A (en) * 1992-05-29 1994-05-10 Sgs-Thomson Microelectronics, Inc. Method of forming a MOSFET structure with planar surface
US5290718A (en) * 1992-06-29 1994-03-01 National Semiconductor Corporation Simplified high reliability gate oxide process
US5264387A (en) * 1992-10-27 1993-11-23 International Business Machines Corporation Method of forming uniformly thin, isolated silicon mesas on an insulating substrate
US6310384B1 (en) 1993-07-02 2001-10-30 Hitachi, Ltd. Low stress semiconductor devices with thermal oxide isolation
DE4340226C2 (de) * 1993-11-25 2002-03-14 Gold Star Electronics Bauelement mit Isolationsbereichsstruktur und Verfahren zum Herstellen desselben
US6034410A (en) * 1994-01-14 2000-03-07 Stmicroelectronics, Inc. MOSFET structure with planar surface
US5459096A (en) * 1994-07-05 1995-10-17 Motorola Inc. Process for fabricating a semiconductor device using dual planarization layers
KR0176153B1 (ko) * 1995-05-30 1999-04-15 김광호 반도체 장치의 소자분리막 및 그 형성방법
US6008526A (en) * 1995-05-30 1999-12-28 Samsung Electronics Co., Ltd. Device isolation layer for a semiconductor device
KR0186083B1 (ko) * 1995-08-12 1999-04-15 문정환 반도체 소자의 소자격리방법
JP2762973B2 (ja) * 1995-11-30 1998-06-11 日本電気株式会社 半導体装置の製造方法
KR980006053A (ko) * 1996-06-26 1998-03-30 문정환 반도체장치의 격리막 형성방법
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
JP2891205B2 (ja) * 1996-10-21 1999-05-17 日本電気株式会社 半導体集積回路の製造方法
JPH10144785A (ja) * 1996-11-06 1998-05-29 Samsung Electron Co Ltd 半導体装置及びその素子分離方法
KR100226488B1 (ko) * 1996-12-26 1999-10-15 김영환 반도체 소자 격리구조 및 그 형성방법
JP3547279B2 (ja) * 1997-02-18 2004-07-28 株式会社ルネサステクノロジ 半導体装置の製造方法
US5728621A (en) * 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation
US5783476A (en) * 1997-06-26 1998-07-21 Siemens Aktiengesellschaft Integrated circuit devices including shallow trench isolation
KR100444315B1 (ko) * 1997-06-28 2004-11-09 주식회사 하이닉스반도체 반도체소자의소자분리막형성방법
US5834359A (en) * 1997-08-29 1998-11-10 Vanguard International Semiconductor Corporation Method of forming an isolation region in a semiconductor substrate
US5976950A (en) * 1997-11-13 1999-11-02 National Semiconductor Corporation Polysilicon coated swami (sidewall masked isolation)
US6118167A (en) * 1997-11-13 2000-09-12 National Semiconductor Corporation Polysilicon coated nitride-lined shallow trench
US6228746B1 (en) * 1997-12-18 2001-05-08 Advanced Micro Devices, Inc. Methodology for achieving dual field oxide thicknesses
US5998280A (en) * 1998-03-20 1999-12-07 National Semiconductor Corporation Modified recessed locos isolation process for deep sub-micron device processes
US6087214A (en) * 1998-04-29 2000-07-11 Vlsi Technology, Inc. Arrangement and method for DRAM cell using shallow trench isolation
US6127215A (en) * 1998-10-29 2000-10-03 International Business Machines Corp. Deep pivot mask for enhanced buried-channel PFET performance and reliability
US6060348A (en) * 1998-11-02 2000-05-09 Vanguard International Semiconducter Corporation Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology
JP3751469B2 (ja) * 1999-04-26 2006-03-01 沖電気工業株式会社 Ｓｏｉ構造の半導体装置の製造方法
US6300220B1 (en) * 2000-01-06 2001-10-09 National Semiconductor Corporation Process for fabricating isolation structure for IC featuring grown and buried field oxide
US6727161B2 (en) 2000-02-16 2004-04-27 Cypress Semiconductor Corp. Isolation technology for submicron semiconductor devices
US20070281403A1 (en) * 2006-06-01 2007-12-06 Mon-Chin Tsai Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing
US20140272684A1 (en) * 2013-03-12 2014-09-18 Applied Materials, Inc. Extreme ultraviolet lithography mask blank manufacturing system and method of operation therefor
US9632411B2 (en) 2013-03-14 2017-04-25 Applied Materials, Inc. Vapor deposition deposited photoresist, and manufacturing and lithography systems therefor
US9354508B2 (en) 2013-03-12 2016-05-31 Applied Materials, Inc. Planarized extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor
CN107700106A (zh) * 2017-11-20 2018-02-16 广州市番禺区沙湾同心机器厂 一种洗染设备及其滚筒结构
US10529812B1 (en) * 2018-10-10 2020-01-07 Texas Instruments Incorporated Locos with sidewall spacer for transistors and other devices

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
US4508757A (en) * 1982-12-20 1985-04-02 International Business Machines Corporation Method of manufacturing a minimum bird's beak recessed oxide isolation structure
JPS59124141A (ja) * 1982-12-28 1984-07-18 Toshiba Corp 半導体装置の製造方法
JPS59125638A (ja) * 1983-01-05 1984-07-20 Nec Corp 半導体素子分離の製造方法
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures

Also Published As

Publication number Publication date
EP0252450A3 (de) 1989-10-25
CN1013160B (zh) 1991-07-10
CN87104640A (zh) 1988-01-27
EP0252450A2 (de) 1988-01-13
JPS6340337A (ja) 1988-02-20
DE3751920T2 (de) 1997-02-13
EP0252450B1 (de) 1996-10-09
KR880002255A (ko) 1988-04-30
KR960016502B1 (ko) 1996-12-12
US4842675A (en) 1989-06-27

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