DE3851125D1 - Verfahren zur Herstellung eines Halbleiterbauelementes mit Schaltungsmaterial gefüllter Rille. - Google Patents
Verfahren zur Herstellung eines Halbleiterbauelementes mit Schaltungsmaterial gefüllter Rille.Info
- Publication number
- DE3851125D1 DE3851125D1 DE3851125T DE3851125T DE3851125D1 DE 3851125 D1 DE3851125 D1 DE 3851125D1 DE 3851125 T DE3851125 T DE 3851125T DE 3851125 T DE3851125 T DE 3851125T DE 3851125 D1 DE3851125 D1 DE 3851125D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- circuit material
- groove filled
- filled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62265943A JPH01108746A (ja) | 1987-10-21 | 1987-10-21 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3851125D1 true DE3851125D1 (de) | 1994-09-22 |
DE3851125T2 DE3851125T2 (de) | 1995-02-23 |
Family
ID=17424236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3851125T Expired - Lifetime DE3851125T2 (de) | 1987-10-21 | 1988-10-21 | Verfahren zur Herstellung eines Halbleiterbauelementes mit Schaltungsmaterial gefüllter Rille. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4876223A (de) |
EP (1) | EP0316612B1 (de) |
JP (1) | JPH01108746A (de) |
KR (1) | KR920003307B1 (de) |
DE (1) | DE3851125T2 (de) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5256565A (en) * | 1989-05-08 | 1993-10-26 | The United States Of America As Represented By The United States Department Of Energy | Electrochemical planarization |
DE4028776C2 (de) * | 1990-07-03 | 1994-03-10 | Samsung Electronics Co Ltd | Verfahren zur Bildung einer metallischen Verdrahtungsschicht und Füllen einer Kontaktöffnung in einem Halbleiterbauelement |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
DE4200809C2 (de) * | 1991-03-20 | 1996-12-12 | Samsung Electronics Co Ltd | Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US6355553B1 (en) * | 1992-07-21 | 2002-03-12 | Sony Corporation | Method of forming a metal plug in a contact hole |
DE69323513T2 (de) * | 1992-07-27 | 1999-08-12 | St Microelectronics Inc | Planaxer Kontakt mit einer Lücke |
JP2885616B2 (ja) * | 1992-07-31 | 1999-04-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP3382357B2 (ja) * | 1993-08-27 | 2003-03-04 | ヤマハ株式会社 | 配線形成方法 |
US5776827A (en) * | 1993-08-27 | 1998-07-07 | Yamaha Corporation | Wiring-forming method |
JP2947054B2 (ja) * | 1994-03-04 | 1999-09-13 | ヤマハ株式会社 | 配線形成法 |
JP3104534B2 (ja) * | 1994-06-27 | 2000-10-30 | ヤマハ株式会社 | 半導体装置とその製法 |
US5459096A (en) * | 1994-07-05 | 1995-10-17 | Motorola Inc. | Process for fabricating a semiconductor device using dual planarization layers |
US7118988B2 (en) * | 1994-08-15 | 2006-10-10 | Buerger Jr Walter Richard | Vertically wired integrated circuit and method of fabrication |
US5981354A (en) * | 1997-03-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process |
KR100268459B1 (ko) * | 1998-05-07 | 2000-10-16 | 윤종용 | 반도체 장치의 콘택 플러그 형성 방법 |
KR100546296B1 (ko) * | 1999-08-06 | 2006-01-26 | 삼성전자주식회사 | 금속 브리지를 방지하는 반도체 장치의 금속 배선 제조 방법 |
US6410442B1 (en) * | 1999-08-18 | 2002-06-25 | Advanced Micro Devices, Inc. | Mask-less differential etching and planarization of copper films |
US6696358B2 (en) * | 2001-01-23 | 2004-02-24 | Honeywell International Inc. | Viscous protective overlayers for planarization of integrated circuits |
US7700533B2 (en) * | 2005-06-23 | 2010-04-20 | Air Products And Chemicals, Inc. | Composition for removal of residue comprising cationic salts and methods using same |
JP2010016240A (ja) * | 2008-07-04 | 2010-01-21 | Panasonic Corp | インダクタとその製造方法 |
CN102820227B (zh) * | 2011-06-08 | 2015-08-19 | 无锡华润上华半导体有限公司 | 一种深沟槽超级pn结的形成方法 |
US9269612B2 (en) * | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
CN103077924A (zh) * | 2013-01-15 | 2013-05-01 | 江苏物联网研究发展中心 | 倒置浸入式晶圆平坦化的方法 |
CN105633005A (zh) * | 2014-10-30 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | 铜互连结构的制作方法 |
KR20220024438A (ko) * | 2019-06-18 | 2022-03-03 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법 및 기판 처리 장치 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2041558B (en) * | 1978-11-29 | 1983-02-09 | Raychem Corp | Light-guide terminations |
US4290668A (en) * | 1978-11-29 | 1981-09-22 | Raychem Corporation | Fiber optic waveguide termination and method of forming same |
FR2566181B1 (fr) * | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre |
US4636282A (en) * | 1985-06-20 | 1987-01-13 | Great Lakes Chemical Corporation | Method for etching copper and composition useful therein |
EP0234407A1 (de) * | 1986-02-28 | 1987-09-02 | General Electric Company | Verfahren zum Auffüllen von Verbindungs- oder Kontaktlöchern in einer mehrlagigen VLSI-Metallisierungsstruktur |
-
1987
- 1987-10-21 JP JP62265943A patent/JPH01108746A/ja active Granted
-
1988
- 1988-10-20 US US07/260,300 patent/US4876223A/en not_active Expired - Lifetime
- 1988-10-21 KR KR1019880013747A patent/KR920003307B1/ko not_active IP Right Cessation
- 1988-10-21 DE DE3851125T patent/DE3851125T2/de not_active Expired - Lifetime
- 1988-10-21 EP EP88117590A patent/EP0316612B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0434295B2 (de) | 1992-06-05 |
KR890007373A (ko) | 1989-06-19 |
EP0316612B1 (de) | 1994-08-17 |
DE3851125T2 (de) | 1995-02-23 |
EP0316612A2 (de) | 1989-05-24 |
KR920003307B1 (ko) | 1992-04-27 |
JPH01108746A (ja) | 1989-04-26 |
US4876223A (en) | 1989-10-24 |
EP0316612A3 (de) | 1991-01-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |