DE3851380T2 - Statische Ram-Zelle mit an Masse verbundene Graben-Transistoren und vergrabene Masseschicht. - Google Patents

Statische Ram-Zelle mit an Masse verbundene Graben-Transistoren und vergrabene Masseschicht.

Info

Publication number
DE3851380T2
DE3851380T2 DE3851380T DE3851380T DE3851380T2 DE 3851380 T2 DE3851380 T2 DE 3851380T2 DE 3851380 T DE3851380 T DE 3851380T DE 3851380 T DE3851380 T DE 3851380T DE 3851380 T2 DE3851380 T2 DE 3851380T2
Authority
DE
Germany
Prior art keywords
ground
static ram
transistors connected
ram cell
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3851380T
Other languages
English (en)
Other versions
DE3851380D1 (de
Inventor
Fu-Chieh Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics America Inc
Original Assignee
Integrated Device Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Device Technology Inc filed Critical Integrated Device Technology Inc
Application granted granted Critical
Publication of DE3851380D1 publication Critical patent/DE3851380D1/de
Publication of DE3851380T2 publication Critical patent/DE3851380T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
DE3851380T 1987-07-02 1988-06-14 Statische Ram-Zelle mit an Masse verbundene Graben-Transistoren und vergrabene Masseschicht. Expired - Fee Related DE3851380T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/069,168 US4794561A (en) 1987-07-02 1987-07-02 Static ram cell with trench pull-down transistors and buried-layer ground plate

Publications (2)

Publication Number Publication Date
DE3851380D1 DE3851380D1 (de) 1994-10-13
DE3851380T2 true DE3851380T2 (de) 1995-04-06

Family

ID=22087183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3851380T Expired - Fee Related DE3851380T2 (de) 1987-07-02 1988-06-14 Statische Ram-Zelle mit an Masse verbundene Graben-Transistoren und vergrabene Masseschicht.

Country Status (4)

Country Link
US (1) US4794561A (de)
EP (1) EP0297350B1 (de)
JP (1) JPS6435948A (de)
DE (1) DE3851380T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890144A (en) * 1987-09-14 1989-12-26 Motorola, Inc. Integrated circuit trench cell
US5194749A (en) * 1987-11-30 1993-03-16 Hitachi, Ltd. Semiconductor integrated circuit device
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5227649A (en) * 1989-02-27 1993-07-13 Texas Instruments Incorporated Circuit layout and method for VLSI circuits having local interconnects
US5016070A (en) * 1989-06-30 1991-05-14 Texas Instruments Incorporated Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors
JPH0513714A (ja) * 1990-01-25 1993-01-22 Texas Instr Inc <Ti> 溝型トランジスタ使用の双安定論理デバイス
US5241204A (en) * 1990-07-25 1993-08-31 Sony Corporation Semiconductor memory
US5145799A (en) * 1991-01-30 1992-09-08 Texas Instruments Incorporated Stacked capacitor SRAM cell
TW208088B (de) * 1991-05-16 1993-06-21 American Telephone & Telegraph
DE69233383T2 (de) * 1991-06-03 2005-08-18 STMicroelectronics, Inc., Carrollton Sram-Zelle und Struktur, beinhaltend polykristalline Lastelemente mit P-leitendem Kanal
EP0550177B1 (de) * 1991-12-30 2002-04-10 AT&T Corp. Statischer RAM-Speicher mit abgeglichenem Widerstand in einer integrierten Schaltung
JP2572194B2 (ja) * 1993-06-18 1997-01-16 日機装株式会社 靴下仕上用型板
US5354704A (en) * 1993-07-28 1994-10-11 United Microelectronics Corporation Symmetric SRAM cell with buried N+ local interconnection line
US5394358A (en) * 1994-03-28 1995-02-28 Vlsi Technology, Inc. SRAM memory cell with tri-level local interconnect
US5698893A (en) * 1995-01-03 1997-12-16 Motorola, Inc. Static-random-access memory cell with trench transistor and enhanced stability
US5670803A (en) * 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
JP2959129B2 (ja) * 1995-07-31 1999-10-06 日本鋼管株式会社 Ｓｒａｍ装置およびその製造方法
TW424326B (en) * 1997-11-27 2001-03-01 Siemens Ag SRAM-cells arrangement and its production method
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
KR100398577B1 (ko) * 2001-08-24 2003-09-19 주식회사 하이닉스반도체 정적 노이즈 마진을 향상시킨 반도체 장치의 제조 방법
US7919800B2 (en) 2007-02-26 2011-04-05 Micron Technology, Inc. Capacitor-less memory cells and cell arrays
US8982649B2 (en) 2011-08-12 2015-03-17 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
US9318174B1 (en) 2013-03-15 2016-04-19 Gsi Technology, Inc. Memory systems and methods involving high speed local address circuitry
US9564441B2 (en) 2014-09-25 2017-02-07 Kilopass Technology, Inc. Two-transistor SRAM semiconductor structure and methods of fabrication
US9741413B2 (en) 2014-09-25 2017-08-22 Kilopass Technology, Inc. Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
US20160093624A1 (en) 2014-09-25 2016-03-31 Kilopass Technology, Inc. Thyristor Volatile Random Access Memory and Methods of Manufacture
US9613968B2 (en) 2014-09-25 2017-04-04 Kilopass Technology, Inc. Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
US9460771B2 (en) 2014-09-25 2016-10-04 Kilopass Technology, Inc. Two-transistor thyristor SRAM circuit and methods of operation
US9564199B2 (en) 2014-09-25 2017-02-07 Kilopass Technology, Inc. Methods of reading and writing data in a thyristor random access memory
US9530482B2 (en) 2014-09-25 2016-12-27 Kilopass Technology, Inc. Methods of retaining and refreshing data in a thyristor random access memory
US9449669B2 (en) 2014-09-25 2016-09-20 Kilopass Technology, Inc. Cross-coupled thyristor SRAM circuits and methods of operation
US9922700B2 (en) * 2016-05-24 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Memory read stability enhancement with short segmented bit line architecture
US11018142B2 (en) * 2018-07-16 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4252579A (en) * 1979-05-07 1981-02-24 International Business Machines Corporation Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition
JPS5858755A (ja) * 1982-09-06 1983-04-07 Hitachi Ltd 半導体回路装置
JPS60161659A (ja) * 1984-02-01 1985-08-23 Hitachi Ltd 半導体集積回路装置
JPS60239052A (ja) * 1984-05-14 1985-11-27 Hitachi Ltd 半導体集積回路装置
JPS60261167A (ja) * 1984-06-08 1985-12-24 Hitachi Ltd 半導体集積回路装置
JPS615569A (ja) * 1984-06-20 1986-01-11 Hitachi Ltd 半導体装置
US4721987A (en) * 1984-07-03 1988-01-26 Texas Instruments Incorporated Trench capacitor process for high density dynamic RAM
JPS61263257A (ja) * 1985-05-17 1986-11-21 Matsushita Electric Ind Co Ltd 半導体装置

Also Published As

Publication number Publication date
DE3851380D1 (de) 1994-10-13
US4794561A (en) 1988-12-27
EP0297350A2 (de) 1989-01-04
EP0297350A3 (en) 1989-11-29
JPS6435948A (en) 1989-02-07
EP0297350B1 (de) 1994-09-07

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee