DE3855389D1 - System und Verfahren zur Ermittlung des Zentrums eines integrierten Schaltungsplättchens - Google Patents

System und Verfahren zur Ermittlung des Zentrums eines integrierten Schaltungsplättchens

Info

Publication number
DE3855389D1
DE3855389D1 DE3855389T DE3855389T DE3855389D1 DE 3855389 D1 DE3855389 D1 DE 3855389D1 DE 3855389 T DE3855389 T DE 3855389T DE 3855389 T DE3855389 T DE 3855389T DE 3855389 D1 DE3855389 D1 DE 3855389D1
Authority
DE
Germany
Prior art keywords
determining
center
integrated circuit
circuit die
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855389T
Other languages
English (en)
Other versions
DE3855389T2 (de
Inventor
David Cheng
Wesley W Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of DE3855389D1 publication Critical patent/DE3855389D1/de
Application granted granted Critical
Publication of DE3855389T2 publication Critical patent/DE3855389T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00Material or article handling
    • Y10S414/135Associated with semiconductor wafer handling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00Material or article handling
    • Y10S414/135Associated with semiconductor wafer handling
    • Y10S414/137Associated with semiconductor wafer handling including means for charging or discharging wafer cassette
DE3855389T 1987-04-20 1988-04-18 System und Verfahren zur Ermittlung des Zentrums eines integrierten Schaltungsplättchens Expired - Fee Related DE3855389T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/040,974 US4819167A (en) 1987-04-20 1987-04-20 System and method for detecting the center of an integrated circuit wafer

Publications (2)

Publication Number Publication Date
DE3855389D1 true DE3855389D1 (de) 1996-08-08
DE3855389T2 DE3855389T2 (de) 1997-01-02

Family

ID=21914022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855389T Expired - Fee Related DE3855389T2 (de) 1987-04-20 1988-04-18 System und Verfahren zur Ermittlung des Zentrums eines integrierten Schaltungsplättchens

Country Status (5)

Country Link
US (1) US4819167A (de)
EP (1) EP0288233B1 (de)
JP (1) JPH0727953B2 (de)
AT (1) ATE140103T1 (de)
DE (1) DE3855389T2 (de)

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EP0288233A3 (de) 1991-01-23
US4819167A (en) 1989-04-04
JPH0727953B2 (ja) 1995-03-29
EP0288233A2 (de) 1988-10-26
ATE140103T1 (de) 1996-07-15
DE3855389T2 (de) 1997-01-02
JPS6448443A (en) 1989-02-22
EP0288233B1 (de) 1996-07-03

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