DE3856175D1 - Digitales Signalverarbeitungssystem in dem ein Prozessor unter Kontrolle eines Hosts auf zwei Befehlsspeicher zugreift - Google Patents

Digitales Signalverarbeitungssystem in dem ein Prozessor unter Kontrolle eines Hosts auf zwei Befehlsspeicher zugreift

Info

Publication number
DE3856175D1
DE3856175D1 DE3856175T DE3856175T DE3856175D1 DE 3856175 D1 DE3856175 D1 DE 3856175D1 DE 3856175 T DE3856175 T DE 3856175T DE 3856175 T DE3856175 T DE 3856175T DE 3856175 D1 DE3856175 D1 DE 3856175D1
Authority
DE
Germany
Prior art keywords
host
signal processing
processing system
digital signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3856175T
Other languages
English (en)
Other versions
DE3856175T2 (de
Inventor
Tokumichi Murakami
Koh Kamizawa
Yoshiaki Katoh
Hideo Ohira
Masatoshi Kameyama
Naoto Kinjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14087287A external-priority patent/JPS63304344A/ja
Priority claimed from JP18685887A external-priority patent/JPS6429932A/ja
Priority claimed from JP19700987A external-priority patent/JPS6441028A/ja
Priority claimed from JP62273763A external-priority patent/JPH0630056B2/ja
Priority claimed from JP27481087A external-priority patent/JPH01116730A/ja
Priority claimed from JP62296612A external-priority patent/JPH0766328B2/ja
Priority claimed from JP62296611A external-priority patent/JPH0766327B2/ja
Priority claimed from JP31655387A external-priority patent/JPH01156825A/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3856175D1 publication Critical patent/DE3856175D1/de
Application granted granted Critical
Publication of DE3856175T2 publication Critical patent/DE3856175T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining
DE3856175T 1987-06-05 1988-06-01 Digitales Signalverarbeitungssystem in dem ein Prozessor unter Kontrolle eines Hosts auf zwei Befehlsspeicher zugreift Expired - Fee Related DE3856175T2 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP14087287A JPS63304344A (ja) 1987-06-05 1987-06-05 マルチポ−トメモリ回路
JP18685887A JPS6429932A (en) 1987-07-27 1987-07-27 Address control system for signal processing
JP19700987A JPS6441028A (en) 1987-08-06 1987-08-06 Interruption processing system
JP62273763A JPH0630056B2 (ja) 1987-10-29 1987-10-29 信号処理装置
JP27481087A JPH01116730A (ja) 1987-10-30 1987-10-30 デイジタル信号処理プロセツサ
JP62296612A JPH0766328B2 (ja) 1987-11-25 1987-11-25 プロセッサの信号処理方式
JP62296611A JPH0766327B2 (ja) 1987-11-25 1987-11-25 信号処理方法及び装置
JP31655387A JPH01156825A (ja) 1987-12-15 1987-12-15 信号処理用アドレス生成方式

Publications (2)

Publication Number Publication Date
DE3856175D1 true DE3856175D1 (de) 1998-06-10
DE3856175T2 DE3856175T2 (de) 1998-12-17

Family

ID=27573171

Family Applications (4)

Application Number Title Priority Date Filing Date
DE3856220T Expired - Fee Related DE3856220T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor der bedingte Mehrpunkt-Sprungbefehle im Pipelinemodus bearbeitet
DE3856175T Expired - Fee Related DE3856175T2 (de) 1987-06-05 1988-06-01 Digitales Signalverarbeitungssystem in dem ein Prozessor unter Kontrolle eines Hosts auf zwei Befehlsspeicher zugreift
DE3856219T Expired - Fee Related DE3856219T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor mit Adress-Generator für den Zugriff von Daten aus einem Zweidirektionalen Bereich eines Datenspeichers
DE3851858T Expired - Fee Related DE3851858T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE3856220T Expired - Fee Related DE3856220T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor der bedingte Mehrpunkt-Sprungbefehle im Pipelinemodus bearbeitet

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE3856219T Expired - Fee Related DE3856219T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor mit Adress-Generator für den Zugriff von Daten aus einem Zweidirektionalen Bereich eines Datenspeichers
DE3851858T Expired - Fee Related DE3851858T2 (de) 1987-06-05 1988-06-01 Digitaler Signalprozessor.

Country Status (4)

Country Link
US (1) US5045993A (de)
EP (6) EP0551933A3 (de)
CA (1) CA1288169C (de)
DE (4) DE3856220T2 (de)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1311063C (en) * 1988-12-16 1992-12-01 Tokumichi Murakami Digital signal processor
JPH0769791B2 (ja) * 1988-12-21 1995-07-31 三菱電機株式会社 マイクロプロセッサ
JPH0740241B2 (ja) * 1989-01-17 1995-05-01 富士通株式会社 リクエストキャンセル方式
US5237670A (en) * 1989-01-30 1993-08-17 Alantec, Inc. Method and apparatus for data transfer between source and destination modules
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing
US5175863A (en) * 1989-10-23 1992-12-29 International Business Machines Corporation Signal data processing system having independently, simultaneously operable alu and macu
EP0442041A3 (en) * 1990-01-18 1991-09-04 National Semiconductor Corporation Integrated digital signal processor/general purpose cpu with shared internal memory
JPH0444151A (ja) * 1990-06-11 1992-02-13 Omron Corp プロセッサ
JPH0470946A (ja) * 1990-07-04 1992-03-05 Mitsubishi Electric Corp Ｄｍａコントローラを内蔵した処理装置
JP3194193B2 (ja) * 1990-10-31 2001-07-30 カシオ計算機株式会社 信号処理装置
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
US7197623B1 (en) 1991-06-27 2007-03-27 Texas Instruments Incorporated Multiple processor cellular radio
FR2678400B1 (fr) * 1991-06-27 1995-08-04 Texas Instruments France Processeur de protocole destine a l'execution d'un ensemble d'instructions en un nombre reduit d'operation.
JP3201786B2 (ja) * 1991-07-18 2001-08-27 アジレント・テクノロジー株式会社 ディジタル信号処理システムの制御方法
JP3172214B2 (ja) * 1991-09-30 2001-06-04 富士通株式会社 状態モード設定方式
JP2906792B2 (ja) * 1991-11-15 1999-06-21 日本電気株式会社 ディジタルプロセッサ及びその制御方法
EP0545581B1 (de) * 1991-12-06 1999-04-21 National Semiconductor Corporation Integriertes Datenverarbeitungssystem mit CPU-Kern und unabhängigem parallelen, digitalen Signalprozessormodul
US6000026A (en) * 1992-06-22 1999-12-07 Texas Instrument Incorporated Multiple processor apparatus having a protocol processor intended for the execution of a collection of instructions in a reduced number of operations
DE69315630T2 (de) * 1992-07-23 1998-07-16 Rockwell International Corp Datenzugriff in einem RISC-Digitalsignalprozessor
WO1994006075A1 (en) * 1992-08-31 1994-03-17 Fujitsu Limited Method and apparatus for non-numeric character discrimination
US5717908A (en) * 1993-02-25 1998-02-10 Intel Corporation Pattern recognition system using a four address arithmetic logic unit
US5825921A (en) * 1993-03-19 1998-10-20 Intel Corporation Memory transfer apparatus and method useful within a pattern recognition system
FR2708359A1 (fr) * 1993-06-30 1995-02-03 Philips Electronics Nv Procédé pour exploiter un processeur numérique de signal et dispositif mettant en Óoeuvre le procédé.
DE59408784D1 (de) * 1993-08-09 1999-11-04 Siemens Ag Signalverarbeitungseinrichtung
JP3452655B2 (ja) * 1993-09-27 2003-09-29 株式会社日立製作所 ディジタル信号処理プロセッサおよびそれを用いて命令を実行する方法
US5778416A (en) * 1993-12-20 1998-07-07 Motorola, Inc. Parallel process address generator and method
US5590356A (en) * 1994-08-23 1996-12-31 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5835730A (en) * 1996-07-31 1998-11-10 General Instrument Corporation Of Delaware MPEG packet header compression for television modems
WO1998006039A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Disambiguation memory circuit and operating method
WO1998006040A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Architectural support for software pipelining of nested loops
WO1998006042A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Wide instruction unpack method and apparatus
WO1998006038A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Architectural support for software pipelining of loops
US5958048A (en) * 1996-08-07 1999-09-28 Elbrus International Ltd. Architectural support for software pipelining of nested loops
WO1998006041A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Array prefetch apparatus and method
US5880981A (en) * 1996-08-12 1999-03-09 Hitachi America, Ltd. Method and apparatus for reducing the power consumption in a programmable digital signal processor
US6332152B1 (en) * 1997-12-02 2001-12-18 Matsushita Electric Industrial Co., Ltd. Arithmetic unit and data processing unit
TW380245B (en) * 1998-05-18 2000-01-21 Winbond Elelctronics Corp Speech synthesizer and speech synthesis method
US7234100B1 (en) * 2000-09-28 2007-06-19 Intel Corporation Decoder for trellis-based channel encoding
US6662296B1 (en) * 2000-10-02 2003-12-09 International Business Machines Corporation Method and system for testing millicode branch points
JP2002215606A (ja) * 2001-01-24 2002-08-02 Mitsubishi Electric Corp データ処理装置
US20030061464A1 (en) * 2001-06-01 2003-03-27 Catherwood Michael I. Digital signal controller instruction set and architecture
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US7167973B2 (en) * 2001-11-15 2007-01-23 Broadcom Corporation Method and system for performing multi-tests in processors using results to set a register and indexing based on the register
JP2005149297A (ja) * 2003-11-18 2005-06-09 Renesas Technology Corp プロセッサおよびそのアセンブラ
JP4908017B2 (ja) * 2006-02-28 2012-04-04 富士通株式会社 Ｄｍａデータ転送装置及びｄｍａデータ転送方法
US7953958B2 (en) * 2006-09-29 2011-05-31 Mediatek Inc. Architecture for joint detection hardware accelerator
US20090129486A1 (en) * 2007-11-15 2009-05-21 Sequel Technologies, Llc. Systems and methods for providing security communication procesess in a security system
GB2500707B (en) * 2012-03-30 2014-09-17 Cognovo Ltd Multiprocessor system, apparatus and methods
US20150268962A1 (en) * 2014-03-24 2015-09-24 GoofyFoot Labs Asynchronous Circuit Design
US11847427B2 (en) 2015-04-04 2023-12-19 Texas Instruments Incorporated Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor
US9817791B2 (en) * 2015-04-04 2017-11-14 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word
US10401412B2 (en) 2016-12-16 2019-09-03 Texas Instruments Incorporated Line fault signature analysis
US11010953B2 (en) * 2017-04-21 2021-05-18 Intel Corporation Dedicated fixed point blending for energy efficiency
CN109714056B (zh) * 2019-01-17 2022-10-28 上海双微导航技术有限公司 一种用于兼容多款ad采集的方法
CN110737618B (zh) * 2019-10-23 2021-03-16 盛科网络（苏州）有限公司 内嵌处理器进行快速数据通信的方法、装置及存储介质

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3570006A (en) * 1968-01-02 1971-03-09 Honeywell Inc Multiple branch technique
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US4090250A (en) * 1976-09-30 1978-05-16 Raytheon Company Digital signal processor
DE2710671A1 (de) * 1977-03-11 1978-09-14 Standard Elektrik Lorenz Ag Schaltungsanordnung fuer einen mikroprozessor zur steuerung des datenspeicherzugriffs
US4240139A (en) * 1977-09-22 1980-12-16 Tokyo Shibaura Denki Kabushiki Kaisha Address generating system
FR2407520B1 (fr) * 1977-10-25 1989-05-12 Digital Equipment Corp Unite de traitement centrale pour l'execution d'instructions avec un specificateur d'operande special
US4159519A (en) * 1977-11-21 1979-06-26 Burroughs Corporation Template family interfacing structure for providing a sequence of microinstructions to a pipelined microprogrammable data processing system
US4236206A (en) * 1978-10-25 1980-11-25 Digital Equipment Corporation Central processor unit for executing instructions of variable length
US4428046A (en) * 1980-05-05 1984-01-24 Ncr Corporation Data processing system having a star coupler with contention circuitry
US4493019A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Pipelined microprogrammed digital data processor employing microinstruction tasking
JPS5750052A (en) * 1980-09-09 1982-03-24 Toshiba Corp Address extension system
US4439839A (en) * 1981-08-24 1984-03-27 International Telephone And Telegraph Corporation Dynamically programmable processing element
US4654783A (en) * 1982-07-26 1987-03-31 Data General Corporation Unique process for loading a microcode control store in a data processing system
JPS5979349A (ja) * 1982-10-29 1984-05-08 Toshiba Corp 演算装置
US4613935A (en) * 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit
JPS59174948A (ja) * 1983-03-25 1984-10-03 Toshiba Corp 情報処理装置
US4578750A (en) * 1983-08-24 1986-03-25 Amdahl Corporation Code determination using half-adder based operand comparator
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip

Also Published As

Publication number Publication date
EP0554917B1 (de) 1998-05-06
EP0554917A3 (de) 1994-04-13
EP0551933A2 (de) 1993-07-21
EP0551932A2 (de) 1993-07-21
EP0551932A3 (en) 1993-12-15
EP0551931A2 (de) 1993-07-21
DE3856219T2 (de) 1998-11-19
EP0293851B1 (de) 1994-10-19
DE3856220D1 (de) 1998-08-20
EP0551934A2 (de) 1993-07-21
EP0293851A2 (de) 1988-12-07
DE3851858T2 (de) 1995-05-24
CA1288169C (en) 1991-08-27
EP0551934A3 (de) 1994-04-13
DE3851858D1 (de) 1994-11-24
EP0293851A3 (en) 1990-05-09
DE3856175T2 (de) 1998-12-17
US5045993A (en) 1991-09-03
EP0551932B1 (de) 1998-07-15
EP0551931B1 (de) 1998-07-15
EP0551933A3 (en) 1993-12-15
DE3856220T2 (de) 1999-01-07
DE3856219D1 (de) 1998-08-20
EP0551931A3 (en) 1993-12-15
EP0554917A2 (de) 1993-08-11

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