DE3856439D1 - Halbleiteranordnung mit einer zusammengesetzten isolierenden Zwischenschicht - Google Patents

Halbleiteranordnung mit einer zusammengesetzten isolierenden Zwischenschicht

Info

Publication number
DE3856439D1
DE3856439D1 DE3856439T DE3856439T DE3856439D1 DE 3856439 D1 DE3856439 D1 DE 3856439D1 DE 3856439 T DE3856439 T DE 3856439T DE 3856439 T DE3856439 T DE 3856439T DE 3856439 D1 DE3856439 D1 DE 3856439D1
Authority
DE
Germany
Prior art keywords
intermediate layer
semiconductor arrangement
composite insulating
insulating intermediate
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3856439T
Other languages
English (en)
Other versions
DE3856439T2 (de
Inventor
Yasukazu Mase
Masahiro Abe
Tomie Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3856439D1 publication Critical patent/DE3856439D1/de
Application granted granted Critical
Publication of DE3856439T2 publication Critical patent/DE3856439T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
DE3856439T 1987-11-30 1988-11-30 Halbleiteranordnung mit einer zusammengesetzten isolierenden Zwischenschicht Expired - Fee Related DE3856439T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62302604A JPH0654774B2 (ja) 1987-11-30 1987-11-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE3856439D1 true DE3856439D1 (de) 2000-12-07
DE3856439T2 DE3856439T2 (de) 2001-03-29

Family

ID=17910980

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3856439T Expired - Fee Related DE3856439T2 (de) 1987-11-30 1988-11-30 Halbleiteranordnung mit einer zusammengesetzten isolierenden Zwischenschicht

Country Status (5)

Country Link
US (1) US5055906A (de)
EP (1) EP0318954B1 (de)
JP (1) JPH0654774B2 (de)
KR (1) KR910009803B1 (de)
DE (1) DE3856439T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
GB2279804A (en) * 1993-07-02 1995-01-11 Plessey Semiconductors Ltd Insulating layers for multilayer wiring
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
EP0696056B1 (de) * 1994-07-29 2000-01-19 STMicroelectronics, Inc. Verfahren zum Testen und Reparieren eines integrierten Schaltkreises und zum Herstellen einer Passivierungsstruktur
JPH08162528A (ja) * 1994-10-03 1996-06-21 Sony Corp 半導体装置の層間絶縁膜構造
US5563762A (en) * 1994-11-28 1996-10-08 Northern Telecom Limited Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
US5814529A (en) * 1995-01-17 1998-09-29 Semiconductor Energy Laboratory Co., Ltd. Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
DE19540309A1 (de) * 1995-10-28 1997-04-30 Philips Patentverwaltung Halbleiterbauelement mit Passivierungsaufbau
US5940732A (en) 1995-11-27 1999-08-17 Semiconductor Energy Laboratory Co., Method of fabricating semiconductor device
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US7038239B2 (en) 2002-04-09 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
JP3989761B2 (ja) 2002-04-09 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
JP3989763B2 (ja) 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
TWI270919B (en) 2002-04-15 2007-01-11 Semiconductor Energy Lab Display device and method of fabricating the same
US7256421B2 (en) 2002-05-17 2007-08-14 Semiconductor Energy Laboratory, Co., Ltd. Display device having a structure for preventing the deterioration of a light emitting device
JP5118300B2 (ja) * 2005-12-20 2013-01-16 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20110079908A1 (en) * 2009-10-06 2011-04-07 Unisem Advanced Technologies Sdn. Bhd. Stress buffer to protect device features

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605061B2 (ja) * 1975-09-29 1985-02-08 シチズン時計株式会社 集積化容量素子の製造方法
JPS601846A (ja) * 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
JPS6030153A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 半導体装置
US4654113A (en) * 1984-02-10 1987-03-31 Fujitsu Limited Process for fabricating a semiconductor device
JPS60206161A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体集積回路
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
JPS6370567A (ja) * 1986-09-12 1988-03-30 Nippon Telegr & Teleph Corp <Ntt> 有機トンネル素子

Also Published As

Publication number Publication date
EP0318954A2 (de) 1989-06-07
KR910009803B1 (ko) 1991-11-30
JPH0654774B2 (ja) 1994-07-20
EP0318954A3 (de) 1989-07-26
US5055906A (en) 1991-10-08
EP0318954B1 (de) 2000-11-02
KR890008976A (ko) 1989-07-13
JPH01144632A (ja) 1989-06-06
DE3856439T2 (de) 2001-03-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee