DE3877282D1 - Verfahren zum herstellen einer halbleiter-vorrichtung. - Google Patents
Verfahren zum herstellen einer halbleiter-vorrichtung.Info
- Publication number
- DE3877282D1 DE3877282D1 DE8888306979T DE3877282T DE3877282D1 DE 3877282 D1 DE3877282 D1 DE 3877282D1 DE 8888306979 T DE8888306979 T DE 8888306979T DE 3877282 T DE3877282 T DE 3877282T DE 3877282 D1 DE3877282 D1 DE 3877282D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62188241A JPH06105772B2 (ja) | 1987-07-28 | 1987-07-28 | 半導体装置の製造方法 |
JP63036767A JPH0682659B2 (ja) | 1988-02-19 | 1988-02-19 | 半導体集積回路の配線構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3877282D1 true DE3877282D1 (de) | 1993-02-18 |
DE3877282T2 DE3877282T2 (de) | 1993-07-29 |
Family
ID=26375859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8888306979T Expired - Lifetime DE3877282T2 (de) | 1987-07-28 | 1988-07-28 | Verfahren zum herstellen einer halbleiter-vorrichtung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5110766A (de) |
EP (1) | EP0305055B1 (de) |
KR (1) | KR920000077B1 (de) |
DE (1) | DE3877282T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5602056A (en) * | 1990-03-05 | 1997-02-11 | Vlsi Technology, Inc. | Method for forming reliable MOS devices using silicon rich plasma oxide film |
US5763937A (en) * | 1990-03-05 | 1998-06-09 | Vlsi Technology, Inc. | Device reliability of MOS devices using silicon rich plasma oxide films |
US5374833A (en) * | 1990-03-05 | 1994-12-20 | Vlsi Technology, Inc. | Structure for suppression of field inversion caused by charge build-up in the dielectric |
JPH04342164A (ja) * | 1991-05-20 | 1992-11-27 | Hitachi Ltd | 半導体集積回路装置の形成方法 |
JP3216104B2 (ja) * | 1991-05-29 | 2001-10-09 | ソニー株式会社 | メタルプラグ形成方法及び配線形成方法 |
JP2689038B2 (ja) * | 1991-12-04 | 1997-12-10 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5414221A (en) | 1991-12-31 | 1995-05-09 | Intel Corporation | Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias |
US5220483A (en) * | 1992-01-16 | 1993-06-15 | Crystal Semiconductor | Tri-level capacitor structure in switched-capacitor filter |
US5250464A (en) * | 1992-03-11 | 1993-10-05 | Texas Instruments Incorporated | Method of making a low capacitance, low resistance sidewall antifuse structure |
US5500557A (en) * | 1992-04-30 | 1996-03-19 | Sgs-Thomson Microelectronics, Inc. | Structure and method for fabricating integrated circuits |
US5576225A (en) * | 1992-05-09 | 1996-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming electric circuit using anodic oxidation |
US5229326A (en) * | 1992-06-23 | 1993-07-20 | Micron Technology, Inc. | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
USRE40790E1 (en) | 1992-06-23 | 2009-06-23 | Micron Technology, Inc. | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
DE69333722T2 (de) * | 1993-05-31 | 2005-12-08 | Stmicroelectronics S.R.L., Agrate Brianza | Verfahren zur Verbesserung der Haftung zwischen Dielektrikschichten, an ihrer Grenzfläche, in der Herstellung von Halbleiterbauelementen |
US5534451A (en) * | 1995-04-27 | 1996-07-09 | Taiwan Semiconductor Manufacturing Company | Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57126147A (en) * | 1981-01-28 | 1982-08-05 | Fujitsu Ltd | Manufacture of semiconductor device |
US4453306A (en) * | 1983-05-27 | 1984-06-12 | At&T Bell Laboratories | Fabrication of FETs |
KR890004962B1 (ko) * | 1985-02-08 | 1989-12-02 | 가부시끼가이샤 도오시바 | 반도체장치 및 그 제조방법 |
KR900003618B1 (ko) * | 1986-05-30 | 1990-05-26 | 후지쓰가부시끼가이샤 | 반도체장치 및 그 제조방법 |
US4894351A (en) * | 1988-02-16 | 1990-01-16 | Sprague Electric Company | Method for making a silicon IC with planar double layer metal conductors system |
US4874493A (en) * | 1988-03-28 | 1989-10-17 | Microelectronics And Computer Technology Corporation | Method of deposition of metal into cavities on a substrate |
-
1988
- 1988-07-27 KR KR1019880009514A patent/KR920000077B1/ko not_active IP Right Cessation
- 1988-07-28 DE DE8888306979T patent/DE3877282T2/de not_active Expired - Lifetime
- 1988-07-28 EP EP88306979A patent/EP0305055B1/de not_active Expired - Lifetime
-
1990
- 1990-07-06 US US07/549,632 patent/US5110766A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0305055B1 (de) | 1993-01-07 |
KR890003035A (ko) | 1989-04-12 |
DE3877282T2 (de) | 1993-07-29 |
US5110766A (en) | 1992-05-05 |
KR920000077B1 (ko) | 1992-01-06 |
EP0305055A1 (de) | 1989-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |