DE3878654T2 - Signalverzoegerungsverfahren und einstellbare verzoegerungsschaltung. - Google Patents

Signalverzoegerungsverfahren und einstellbare verzoegerungsschaltung.

Info

Publication number
DE3878654T2
DE3878654T2 DE8888117328T DE3878654T DE3878654T2 DE 3878654 T2 DE3878654 T2 DE 3878654T2 DE 8888117328 T DE8888117328 T DE 8888117328T DE 3878654 T DE3878654 T DE 3878654T DE 3878654 T2 DE3878654 T2 DE 3878654T2
Authority
DE
Germany
Prior art keywords
adjustable
signal
delay
delay circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888117328T
Other languages
English (en)
Other versions
DE3878654D1 (de
Inventor
Einar Oddbjorn Traa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC.,
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of DE3878654D1 publication Critical patent/DE3878654D1/de
Application granted granted Critical
Publication of DE3878654T2 publication Critical patent/DE3878654T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means
    • H03K17/6264—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means using current steering means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE8888117328T 1987-11-25 1988-10-18 Signalverzoegerungsverfahren und einstellbare verzoegerungsschaltung. Expired - Fee Related DE3878654T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/125,023 US4797586A (en) 1987-11-25 1987-11-25 Controllable delay circuit

Publications (2)

Publication Number Publication Date
DE3878654D1 DE3878654D1 (de) 1993-04-01
DE3878654T2 true DE3878654T2 (de) 1993-06-09

Family

ID=22417874

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888117328T Expired - Fee Related DE3878654T2 (de) 1987-11-25 1988-10-18 Signalverzoegerungsverfahren und einstellbare verzoegerungsschaltung.

Country Status (4)

Country Link
US (1) US4797586A (de)
EP (1) EP0317758B1 (de)
JP (1) JPH0638574B2 (de)
DE (1) DE3878654T2 (de)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866314A (en) * 1986-07-18 1989-09-12 Tektronix, Inc. Programmable high-speed digital delay circuit
US4860261A (en) * 1988-02-17 1989-08-22 Intel Corporation Leakage verification for flash EPROM
US4862020A (en) * 1988-06-20 1989-08-29 Tektronix, Inc. Electronic delay control circuit having pulse width maintenance
FR2655218A1 (fr) * 1989-11-28 1991-05-31 Radiotechnique Compelec Circuit retardateur a retard reglable.
US5210450A (en) * 1990-04-16 1993-05-11 Tektronix, Inc. Active selectable digital delay circuit
DE4110340C2 (de) * 1990-04-16 1993-11-25 Tektronix Inc Aktive ansteuerbare digitale Verzögerungsschaltung
JP3077813B2 (ja) * 1990-05-11 2000-08-21 ソニー株式会社 プログラマブル遅延回路
US5063311A (en) * 1990-06-04 1991-11-05 Motorola, Inc. Programmable time delay circuit for digital logic circuits
US5070303A (en) * 1990-08-21 1991-12-03 Telefonaktiebolaget L M Ericsson Logarithmic amplifier/detector delay compensation
DE4140564C2 (de) * 1990-12-10 2000-06-15 Sony Corp Pulssignalgenerator und zugeordnete Kaskodeschaltung
FR2671245B1 (fr) * 1990-12-27 1993-03-05 Bull Sa Dispositif de retard reglable.
FR2671244B1 (fr) * 1990-12-27 1993-03-05 Bull Sa Dispositif de retard reglable.
JP3225527B2 (ja) * 1991-02-22 2001-11-05 ソニー株式会社 遅延回路
US5327021A (en) * 1991-06-10 1994-07-05 Shinko Electric Ind., Co., Ltd. Waveform synthesizing circuit
JP2567361B2 (ja) * 1991-09-13 1996-12-25 東光株式会社 パルス遅延回路
US5157276A (en) * 1991-09-26 1992-10-20 Tektronix, Inc. Low jitter clock phase adjust system
US5175452A (en) * 1991-09-30 1992-12-29 Data Delay Devices, Inc. Programmable compensated digital delay circuit
JP3326619B2 (ja) * 1992-01-08 2002-09-24 ソニー株式会社 Ｐｗｍ回路
EP0553744B1 (de) * 1992-01-31 2001-03-28 Konica Corporation Vorrichtung zur Signalverzögerung
US5554950A (en) * 1992-02-04 1996-09-10 Brooktree Corporation Delay line providing an adjustable delay in response to binary input signals
FR2690022B1 (fr) * 1992-03-24 1997-07-11 Bull Sa Circuit a retard variable.
FR2689339B1 (fr) * 1992-03-24 1996-12-13 Bull Sa Procede et dispositif de reglage de retard a plusieurs gammes.
US5262690A (en) * 1992-04-29 1993-11-16 International Business Machines Corporation Variable delay clock circuit
US5191301A (en) * 1992-05-12 1993-03-02 International Business Machines Corporation Integrated differential voltage controlled ring oscillator
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置
US5650739A (en) * 1992-12-07 1997-07-22 Dallas Semiconductor Corporation Programmable delay lines
US5374860A (en) * 1993-01-15 1994-12-20 National Semiconductor Corporation Multi-tap digital delay line
US5424669A (en) * 1993-04-29 1995-06-13 Texas Instruments Incorporated Digitally controlled output slope control/current limit in power integrated circuits
US5428318A (en) * 1994-02-15 1995-06-27 At&T Corp. Voltage controlled ring oscillator producing a sum output
US5434523A (en) * 1994-04-05 1995-07-18 Motorola, Inc. Circuit and method for adjusting a pulse width of a signal
FR2718903B1 (fr) * 1994-04-13 1996-05-24 Bull Sa Circuit à retard réglable.
US5572159A (en) * 1994-11-14 1996-11-05 Nexgen, Inc. Voltage-controlled delay element with programmable delay
US5777501A (en) * 1996-04-29 1998-07-07 Mosaid Technologies Incorporated Digital delay line for a reduced jitter digital delay lock loop
US5734284A (en) * 1996-10-11 1998-03-31 Northern Telecom Limited RC circuit
US5945863A (en) * 1997-06-18 1999-08-31 Applied Micro Circuits Corporation Analog delay circuit
FR2767982B1 (fr) 1997-09-04 2001-11-23 Sgs Thomson Microelectronics Circuit a retard variable
EP0853385B1 (de) * 1997-11-18 1999-06-23 Hewlett-Packard Company Veränderbare digitale Verzögerungszelle
US6285197B2 (en) 1998-07-31 2001-09-04 Philips Electronics North America Corporation System and method for generating a jittered test signal
CN1159847C (zh) * 1998-12-16 2004-07-28 松下电器产业株式会社 带偏置的比较装置及比较电路
KR100290285B1 (ko) * 1999-01-13 2001-05-15 윤종용 프리스케일러의 입력 버퍼
US6232815B1 (en) * 1999-05-06 2001-05-15 Analog Devices, Inc. ATE pin electronics with complementary waveform drivers
US6489849B1 (en) 1999-12-17 2002-12-03 Analog Devices, Inc. Interpolator having dual transistor ranks and ratiometric control
DE10036863C2 (de) * 2000-07-28 2002-09-19 Texas Instruments Deutschland Treiberschaltung zur Abgabe eines einstellbaren Ausgangssignalstroms
FR2817408B1 (fr) * 2000-11-30 2003-03-21 St Microelectronics Sa Ensemble commandable de sources de courant
US6411145B1 (en) * 2001-06-14 2002-06-25 Lsi Logic Corporation Feedback control of clock duty cycle
US6624688B2 (en) * 2002-01-07 2003-09-23 Intel Corporation Filtering variable offset amplifer
US7446584B2 (en) * 2002-09-25 2008-11-04 Hrl Laboratories, Llc Time delay apparatus and method of using same
WO2005036747A2 (en) * 2003-10-10 2005-04-21 Atmel Corporation Selectable delay pulse generator
EP1560333A3 (de) * 2004-02-02 2007-06-20 Synthesys Research, Inc. Verfahren und Vorrichtung zur Erzeugung variabler Verzögerung
US7061283B1 (en) * 2004-04-30 2006-06-13 Xilinx, Inc. Differential clock driver circuit
US20060164145A1 (en) * 2005-01-21 2006-07-27 Andrei Poskatcheev Method and apparatus for creating variable delay
KR101128557B1 (ko) * 2005-08-23 2012-04-20 ？란 인코포레이티드 신호 에뮬레이션용 방법 및 시스템
US7697827B2 (en) 2005-10-17 2010-04-13 Konicek Jeffrey C User-friendlier interfaces for a camera
JP4829844B2 (ja) * 2007-06-20 2011-12-07 パナソニック株式会社 パルス合成回路
EP2110947B1 (de) * 2008-04-18 2012-07-04 St Microelectronics S.A. HF-Verstärker mit variabler Verstärkung
CN101340146B (zh) * 2008-08-26 2011-03-30 四川和芯微电子股份有限公司 逐级延时电流累加转换速率调节器
US8971447B1 (en) * 2013-10-17 2015-03-03 Fujitsu Limited Variable delay of data signals

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL251041A (de) * 1959-05-01
US3292110A (en) * 1964-09-16 1966-12-13 Bell Telephone Labor Inc Transversal equalizer for digital transmission systems wherein polarity of time-spaced portions of output signal controls corresponding multiplier setting
US3778543A (en) * 1972-09-05 1973-12-11 Ellanin Investments Predictive-retrospective method for bandwidth improvement
US3875522A (en) * 1973-04-13 1975-04-01 Signetics Corp Integrated direct-coupled electronic attenuator
US4434438A (en) * 1981-07-10 1984-02-28 Matsushita Electric Industrial Co., Ltd. Low cost automatic equalizer
US4455534A (en) * 1981-10-30 1984-06-19 Motorola, Inc. Multi-state control circuitry
US4675562A (en) * 1983-08-01 1987-06-23 Fairchild Semiconductor Corporation Method and apparatus for dynamically controlling the timing of signals in automatic test systems
JPS61135217A (ja) * 1984-12-05 1986-06-23 Fujitsu Ltd 可変遅延線

Also Published As

Publication number Publication date
EP0317758A2 (de) 1989-05-31
EP0317758A3 (en) 1989-09-27
US4797586A (en) 1989-01-10
EP0317758B1 (de) 1993-02-24
JPH0638574B2 (ja) 1994-05-18
JPH01170113A (ja) 1989-07-05
DE3878654D1 (de) 1993-04-01

Similar Documents

Publication Publication Date Title
DE3878654T2 (de) Signalverzoegerungsverfahren und einstellbare verzoegerungsschaltung.
DE294214T1 (de) Coexstrusions-vorrichtung und -verfahren.
DE3689538T2 (de) Integrierte Schaltung und Optimierungsverfahren dafür.
DE69019670D1 (de) Verzögerungsmessschaltung.
DE3586081D1 (de) Tonsignalbehandlungsvorrichtung.
DE68926332T2 (de) Verstärkerschaltung
DE3881855T2 (de) Signalverzögerungsschaltung.
DE68920005D1 (de) Signalverarbeitungseinrichtung.
DE3689305D1 (de) Tonsignalsbehandlungsvorrichtung.
DE68901985D1 (de) Verzoegerungsschaltung.
KR870009546A (ko) 지연회로
KR880702004A (ko) 타이밍신호 지연회로장치
DE3861876D1 (de) Vollformverfahren und -vorrichtung.
DE3789813T2 (de) Pulverdiffraktionsverfahren und -vorrichtung.
DE69021616T2 (de) Verzögerungsschaltung.
NO178316C (no) Forsinkelseskrets
DE68906908D1 (de) Signalverarbeitungsschaltung und -verfahren.
DE3751088D1 (de) Signalverarbeitungseinrichtung.
KR890009071A (ko) 증폭기 회로
DE69024711D1 (de) Verstärkerschaltung
DE69024865T2 (de) Verstärkerschaltung
DE69001135T2 (de) Loetverfahren und loetgeraet.
DE68913951D1 (de) Verzögerungsschaltung.
DE3880713T2 (de) Signal-verarbeitungsschaltung.
KR880020712U (ko) 지연 회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC.,

8339 Ceased/non-payment of the annual fee