DE3882489D1 - Pll-schaltung zum generieren eines mit einem eingangssignal mittels eines geschalteten teilers synchronisierten ausgangssignals. - Google Patents

Pll-schaltung zum generieren eines mit einem eingangssignal mittels eines geschalteten teilers synchronisierten ausgangssignals.

Info

Publication number
DE3882489D1
DE3882489D1 DE8888119036T DE3882489T DE3882489D1 DE 3882489 D1 DE3882489 D1 DE 3882489D1 DE 8888119036 T DE8888119036 T DE 8888119036T DE 3882489 T DE3882489 T DE 3882489T DE 3882489 D1 DE3882489 D1 DE 3882489D1
Authority
DE
Germany
Prior art keywords
generating
input signal
pll circuit
output synchronized
switched divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888119036T
Other languages
English (en)
Other versions
DE3882489T2 (de
Inventor
Masashi Arai
Ryuichi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62288822A external-priority patent/JPH01129613A/ja
Priority claimed from JP62292430A external-priority patent/JPH0748657B2/ja
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Application granted granted Critical
Publication of DE3882489D1 publication Critical patent/DE3882489D1/de
Publication of DE3882489T2 publication Critical patent/DE3882489T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
DE88119036T 1987-11-16 1988-11-15 PLL-Schaltung zum Generieren eines mit einem Eingangssignal mittels eines geschalteten Teilers synchronisierten Ausgangssignals. Expired - Lifetime DE3882489T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62288822A JPH01129613A (ja) 1987-11-16 1987-11-16 Ｐｌｌ回路
JP62292430A JPH0748657B2 (ja) 1987-11-19 1987-11-19 Ｐｌｌ回路

Publications (2)

Publication Number Publication Date
DE3882489D1 true DE3882489D1 (de) 1993-08-26
DE3882489T2 DE3882489T2 (de) 1994-02-17

Family

ID=26557347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88119036T Expired - Lifetime DE3882489T2 (de) 1987-11-16 1988-11-15 PLL-Schaltung zum Generieren eines mit einem Eingangssignal mittels eines geschalteten Teilers synchronisierten Ausgangssignals.

Country Status (4)

Country Link
US (1) US4870684A (de)
EP (1) EP0316878B1 (de)
KR (1) KR960008950B1 (de)
DE (1) DE3882489T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097219A (en) * 1988-12-15 1992-03-17 Mitsubishi Denki Kabushiki Kaisha Pll for controlling frequency deviation of a variable frequency oscillator
US4972446A (en) * 1989-08-14 1990-11-20 Delco Electronics Corporation Voltage controlled oscillator using dual modulus divider
US4970474A (en) * 1989-08-14 1990-11-13 Delco Electronics Corporation Analog/digital phase locked loop
DE4006654A1 (de) * 1990-03-03 1991-09-05 Philips Patentverwaltung Schaltungsanordnung zum detektieren von kennschwingungen
FR2680058B1 (fr) * 1991-07-30 1994-01-28 Sgs Thomson Microelectronics Sa Procede et dispositif de synchronisation d'un signal.
US5257301A (en) * 1992-03-30 1993-10-26 Trw Inc. Direct digital frequency multiplier
US5430537A (en) * 1993-09-03 1995-07-04 Dynamics Research Corporation Light beam distance encoder
JP3467888B2 (ja) * 1995-02-08 2003-11-17 三菱電機株式会社 受信装置及び送受信装置
US5815694A (en) * 1995-12-21 1998-09-29 International Business Machines Corporation Apparatus and method to change a processor clock frequency
JPH11203421A (ja) * 1998-01-19 1999-07-30 Oki Electric Ind Co Ltd 半導体ディスク装置
JP3966989B2 (ja) * 1998-04-20 2007-08-29 株式会社東芝 ディスク再生装置及びディスク再生方法
US8456206B2 (en) * 2011-06-20 2013-06-04 Skyworks Solutions, Inc. Phase-locked loop lock detect
JP6813074B1 (ja) * 2019-10-30 2021-01-13 株式会社明電舎 電力変換システム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2413604A1 (de) * 1974-03-21 1975-09-25 Blaupunkt Werke Gmbh Phasenverriegelte regelschleife
JPS5228208A (en) * 1975-08-28 1977-03-03 Nippon Gakki Seizo Kk Fm multiplex stereo demodulator circuit
DE2616398C2 (de) * 1976-04-14 1978-06-01 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur Regelung der Impulsfolgefrequenz eines Signals
DE3463883D1 (en) * 1983-05-27 1987-06-25 Philips Patentverwaltung Television receiver comprising a processing unit for stereophonic/twin sound signal generation
FR2600848B1 (fr) * 1984-09-10 1992-06-05 Labo Cent Telecommunicat Dispositif d'asservissement d'un oscillateur a une source hyperfrequence a tres faible bruit de phase et agile en frequence
US4691175A (en) * 1985-11-14 1987-09-01 Motorola, Inc. Adaptive phase locked loop having a variable locking rate
US4739284A (en) * 1987-05-04 1988-04-19 Motorola, Inc. Phase locked loop having fast frequency lock steering circuit
US4817150A (en) * 1987-08-31 1989-03-28 Rca Licensing Corporation Oscillator frequency control arrangement for a stereo decoder

Also Published As

Publication number Publication date
US4870684A (en) 1989-09-26
EP0316878A3 (en) 1989-08-30
KR960008950B1 (en) 1996-07-10
EP0316878A2 (de) 1989-05-24
DE3882489T2 (de) 1994-02-17
EP0316878B1 (de) 1993-07-21
KR890009107A (ko) 1989-07-15

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