DE3886781D1 - Befehlsdekoder. - Google Patents

Befehlsdekoder.

Info

Publication number
DE3886781D1
DE3886781D1 DE88300196T DE3886781T DE3886781D1 DE 3886781 D1 DE3886781 D1 DE 3886781D1 DE 88300196 T DE88300196 T DE 88300196T DE 3886781 T DE3886781 T DE 3886781T DE 3886781 D1 DE3886781 D1 DE 3886781D1
Authority
DE
Germany
Prior art keywords
command decoder
decoder
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88300196T
Other languages
English (en)
Other versions
DE3886781T2 (de
Inventor
Hiroshi Oki Electric Yokouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE3886781D1 publication Critical patent/DE3886781D1/de
Publication of DE3886781T2 publication Critical patent/DE3886781T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
DE3886781T 1987-01-12 1988-01-12 Befehlsdekoder. Expired - Fee Related DE3886781T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62003305A JP2675779B2 (ja) 1987-01-12 1987-01-12 命令解読装置

Publications (2)

Publication Number Publication Date
DE3886781D1 true DE3886781D1 (de) 1994-02-17
DE3886781T2 DE3886781T2 (de) 1994-06-16

Family

ID=11553646

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3886781T Expired - Fee Related DE3886781T2 (de) 1987-01-12 1988-01-12 Befehlsdekoder.

Country Status (4)

Country Link
US (1) US4958275A (de)
EP (1) EP0275170B1 (de)
JP (1) JP2675779B2 (de)
DE (1) DE3886781T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770961B2 (ja) * 1988-08-12 1995-07-31 日本電気株式会社 マイクロコンピュータ
US5155820A (en) * 1989-02-21 1992-10-13 Gibson Glenn A Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits
US5179691A (en) * 1989-04-12 1993-01-12 Unisys Corporation N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M
US5241637A (en) * 1990-01-05 1993-08-31 Motorola, Inc. Data processor microsequencer having multiple microaddress sources and next microaddress source selection
JPH04140892A (ja) * 1990-02-05 1992-05-14 Internatl Business Mach Corp <Ibm> 制御データをエンコードする装置及び方法
JP2592979B2 (ja) * 1990-04-25 1997-03-19 株式会社東芝 信号処理用集積回路装置
JPH04293124A (ja) * 1991-03-20 1992-10-16 Hitachi Ltd データ処理プロセッサ
JP2520544B2 (ja) * 1991-09-26 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション タスクのオ―バ―ラン状態を監視する方法及びタスク実行サイクルのオ―バ―ランを検出する装置
JP2943464B2 (ja) * 1991-12-09 1999-08-30 松下電器産業株式会社 プログラム制御方法及びプログラム制御装置
US5371864A (en) * 1992-04-09 1994-12-06 International Business Machines Corporation Apparatus for concurrent multiple instruction decode in variable length instruction set computer
US5584031A (en) * 1993-11-09 1996-12-10 Motorola Inc. System and method for executing a low power delay instruction
NL9400607A (nl) * 1994-04-15 1995-11-01 Arcobel Graphics Bv Dataverwerkingscircuit, vermenigvuldigingseenheid met pijplijn, ALU en schuifregistereenheid ten gebruike bij een dataverwerkingscircuit.
US5828875A (en) * 1997-05-29 1998-10-27 Telefonaktiebolaget Lm Ericsson Unroll of instructions in a micro-controller
US6609216B1 (en) 2000-06-16 2003-08-19 International Business Machines Corporation Method for measuring performance of code sequences in a production system
JP3886870B2 (ja) 2002-09-06 2007-02-28 株式会社ルネサステクノロジ データ処理装置
US8161461B2 (en) * 2005-03-24 2012-04-17 Hewlett-Packard Development Company, L.P. Systems and methods for evaluating code usage
US7415599B1 (en) * 2005-11-01 2008-08-19 Zilog, Inc. Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location
US20100023733A1 (en) * 2008-04-15 2010-01-28 Vns Portfolio Llc Microprocessor Extended Instruction Set Precision Mode

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1043358A (en) * 1962-04-02 1966-09-21 Hitachi Ltd Control system for digital computer
US3466613A (en) * 1967-01-13 1969-09-09 Ibm Instruction buffering system
US3665411A (en) * 1970-06-08 1972-05-23 Singer Co Computer
US3771141A (en) * 1971-11-08 1973-11-06 Culler Harrison Inc Data processor with parallel operations per instruction
JPS49116932A (de) * 1973-03-09 1974-11-08
US4118776A (en) * 1975-07-17 1978-10-03 Nippon Electric Company, Ltd. Numerically controlled machine comprising a microprogrammable computer operable with microprograms for macroinstructions and for inherent functions of the machine
US4037213A (en) * 1976-04-23 1977-07-19 International Business Machines Corporation Data processor using a four section instruction format for control of multi-operation functions by a single instruction
US4202035A (en) * 1977-11-25 1980-05-06 Mcdonnell Douglas Corporation Modulo addressing apparatus for use in a microprocessor
US4306287A (en) * 1979-08-31 1981-12-15 Bell Telephone Laboratories, Incorporated Special address generation arrangement
JPS59135549A (ja) * 1983-01-21 1984-08-03 Matsushita Electric Ind Co Ltd 電子計算機装置
JPS59178544A (ja) * 1983-03-30 1984-10-09 Fujitsu Ltd メモリアクセス回路
GB2187577B (en) * 1986-03-07 1989-11-15 Stc Plc Digital computer systems

Also Published As

Publication number Publication date
EP0275170A2 (de) 1988-07-20
JP2675779B2 (ja) 1997-11-12
JPS63172339A (ja) 1988-07-16
EP0275170B1 (de) 1994-01-05
US4958275A (en) 1990-09-18
DE3886781T2 (de) 1994-06-16
EP0275170A3 (en) 1990-04-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee