DE3886899D1 - DRAM-Zelle, die auf einer Isolierschicht gebildet ist und die eine begrabene Halbleiter-Säulenstruktur aufweist und ein Herstellungsverfahren dafür. - Google Patents

DRAM-Zelle, die auf einer Isolierschicht gebildet ist und die eine begrabene Halbleiter-Säulenstruktur aufweist und ein Herstellungsverfahren dafür.

Info

Publication number
DE3886899D1
DE3886899D1 DE88117363T DE3886899T DE3886899D1 DE 3886899 D1 DE3886899 D1 DE 3886899D1 DE 88117363 T DE88117363 T DE 88117363T DE 3886899 T DE3886899 T DE 3886899T DE 3886899 D1 DE3886899 D1 DE 3886899D1
Authority
DE
Germany
Prior art keywords
manufacturing
insulating layer
method therefor
column structure
dram cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88117363T
Other languages
English (en)
Other versions
DE3886899T2 (de
Inventor
Hiroshi Gotou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3886899D1 publication Critical patent/DE3886899D1/de
Application granted granted Critical
Publication of DE3886899T2 publication Critical patent/DE3886899T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
DE3886899T 1987-11-10 1988-10-19 DRAM-Zelle, die auf einer Isolierschicht gebildet ist und die eine begrabene Halbleiter-Säulenstruktur aufweist und ein Herstellungsverfahren dafür. Expired - Fee Related DE3886899T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62283839A JPH01125858A (ja) 1987-11-10 1987-11-10 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE3886899D1 true DE3886899D1 (de) 1994-02-17
DE3886899T2 DE3886899T2 (de) 1994-05-19

Family

ID=17670828

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3886899T Expired - Fee Related DE3886899T2 (de) 1987-11-10 1988-10-19 DRAM-Zelle, die auf einer Isolierschicht gebildet ist und die eine begrabene Halbleiter-Säulenstruktur aufweist und ein Herstellungsverfahren dafür.

Country Status (5)

Country Link
US (1) US5001526A (de)
EP (1) EP0315803B1 (de)
JP (1) JPH01125858A (de)
KR (1) KR910009786B1 (de)
DE (1) DE3886899T2 (de)

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JP2906089B2 (ja) * 1990-12-17 1999-06-14 忠道 政本 ランダム・アクセス・メモリ。
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US5593912A (en) * 1994-10-06 1997-01-14 International Business Machines Corporation SOI trench DRAM cell for 256 MB DRAM and beyond
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US6034389A (en) * 1997-01-22 2000-03-07 International Business Machines Corporation Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
US6337497B1 (en) 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
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US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
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US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
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US6528837B2 (en) 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5914511A (en) * 1997-10-06 1999-06-22 Micron Technology, Inc. Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts
US5907170A (en) * 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
KR100310470B1 (ko) 1997-12-30 2002-05-09 박종섭 양면반도체메모리소자및그제조방법
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
US6137129A (en) 1998-01-05 2000-10-24 International Business Machines Corporation High performance direct coupled FET memory cell
US6297531B2 (en) 1998-01-05 2001-10-02 International Business Machines Corporation High performance, low power vertical integrated CMOS devices
US6025225A (en) * 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US6304483B1 (en) 1998-02-24 2001-10-16 Micron Technology, Inc. Circuits and methods for a static random access memory using vertical transistors
US6246083B1 (en) 1998-02-24 2001-06-12 Micron Technology, Inc. Vertical gain cell and array for a dynamic random access memory
US5963469A (en) * 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6242775B1 (en) 1998-02-24 2001-06-05 Micron Technology, Inc. Circuits and methods using vertical complementary transistors
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US5991225A (en) * 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6043527A (en) * 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US5949700A (en) * 1998-05-26 1999-09-07 International Business Machines Corporation Five square vertical dynamic random access memory cell
US6107133A (en) * 1998-05-28 2000-08-22 International Business Machines Corporation Method for making a five square vertical DRAM cell
US6225158B1 (en) 1998-05-28 2001-05-01 International Business Machines Corporation Trench storage dynamic random access memory cell with vertical transfer device
US5981350A (en) * 1998-05-29 1999-11-09 Micron Technology, Inc. Method for forming high capacitance memory cells
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US6134175A (en) * 1998-08-04 2000-10-17 Micron Technology, Inc. Memory address decode array with vertical transistors
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
KR100268419B1 (ko) * 1998-08-14 2000-10-16 윤종용 고집적 반도체 메모리 장치 및 그의 제조 방법
WO2000019529A1 (de) * 1998-09-25 2000-04-06 Infineon Technologies Ag Integrierte schaltungsanordnung mit vertikaltransistoren und verfahren zu deren herstellung
US6423613B1 (en) 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US5977579A (en) * 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
US6153902A (en) 1999-08-16 2000-11-28 International Business Machines Corporation Vertical DRAM cell with wordline self-aligned to storage trench
US6500744B2 (en) 1999-09-02 2002-12-31 Micron Technology, Inc. Methods of forming DRAM assemblies, transistor devices, and openings in substrates
US6852167B2 (en) * 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
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Also Published As

Publication number Publication date
JPH01125858A (ja) 1989-05-18
EP0315803A3 (en) 1989-07-26
EP0315803B1 (de) 1994-01-05
EP0315803A2 (de) 1989-05-17
KR910009786B1 (ko) 1991-11-30
US5001526A (en) 1991-03-19
KR890008971A (ko) 1989-07-13
DE3886899T2 (de) 1994-05-19

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