DE60002426D1 - Takterzeugung und verteilung in einem emulationssystem - Google Patents

Takterzeugung und verteilung in einem emulationssystem

Info

Publication number
DE60002426D1
DE60002426D1 DE60002426T DE60002426T DE60002426D1 DE 60002426 D1 DE60002426 D1 DE 60002426D1 DE 60002426 T DE60002426 T DE 60002426T DE 60002426 T DE60002426 T DE 60002426T DE 60002426 D1 DE60002426 D1 DE 60002426D1
Authority
DE
Germany
Prior art keywords
clock signal
distribution
emulation system
circuit
clock generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60002426T
Other languages
English (en)
Other versions
DE60002426T2 (de
Inventor
Francois Douezy
Frederic Reblewski
Jean Barbier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Application granted granted Critical
Publication of DE60002426D1 publication Critical patent/DE60002426D1/de
Publication of DE60002426T2 publication Critical patent/DE60002426T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
DE60002426T 1999-09-24 2000-02-08 Takterzeugung und verteilung in einem emulationssystem Expired - Lifetime DE60002426T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/404,923 US6934674B1 (en) 1999-09-24 1999-09-24 Clock generation and distribution in an emulation system
US404923 1999-09-24
PCT/US2000/003261 WO2001024008A1 (en) 1999-09-24 2000-02-08 Clock generation and distribution in an emulation system

Publications (2)

Publication Number Publication Date
DE60002426D1 true DE60002426D1 (de) 2003-06-05
DE60002426T2 DE60002426T2 (de) 2004-03-18

Family

ID=23601588

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60002426T Expired - Lifetime DE60002426T2 (de) 1999-09-24 2000-02-08 Takterzeugung und verteilung in einem emulationssystem

Country Status (7)

Country Link
US (1) US6934674B1 (de)
EP (1) EP1133728B1 (de)
JP (1) JP3537419B2 (de)
AT (1) ATE239251T1 (de)
AU (1) AU2986700A (de)
DE (1) DE60002426T2 (de)
WO (1) WO2001024008A1 (de)

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US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
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US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8516025B2 (en) 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
DE102008009924B4 (de) * 2008-02-15 2014-10-30 Jürgen Altenbrunn Verfahren zum Generieren von Frequenzen
US8229725B1 (en) 2008-09-29 2012-07-24 Xilinx, Inc. Method and apparatus for modeling processor-based circuit models
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
CN101847993B (zh) * 2010-04-29 2015-05-06 北京中星微电子有限公司 一种音频设备的时钟配置方法及系统
US11194943B2 (en) * 2017-12-12 2021-12-07 Synopsys, Inc. FPGA-based hardware emulator system with an inter-FPGA connection switch

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Also Published As

Publication number Publication date
ATE239251T1 (de) 2003-05-15
JP2003501710A (ja) 2003-01-14
EP1133728B1 (de) 2003-05-02
DE60002426T2 (de) 2004-03-18
JP3537419B2 (ja) 2004-06-14
EP1133728A1 (de) 2001-09-19
AU2986700A (en) 2001-04-30
US6934674B1 (en) 2005-08-23
WO2001024008A1 (en) 2001-04-05

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