DE60010674D1 - Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium - Google Patents

Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium

Info

Publication number
DE60010674D1
DE60010674D1 DE60010674T DE60010674T DE60010674D1 DE 60010674 D1 DE60010674 D1 DE 60010674D1 DE 60010674 T DE60010674 T DE 60010674T DE 60010674 T DE60010674 T DE 60010674T DE 60010674 D1 DE60010674 D1 DE 60010674D1
Authority
DE
Germany
Prior art keywords
processor system
speed processor
recording medium
cpu
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60010674T
Other languages
English (en)
Other versions
DE60010674T2 (de
Inventor
Akio Ohba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of DE60010674D1 publication Critical patent/DE60010674D1/de
Application granted granted Critical
Publication of DE60010674T2 publication Critical patent/DE60010674T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
DE60010674T 1999-01-21 2000-01-21 Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium Expired - Lifetime DE60010674T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1348699 1999-01-21
JP1348699 1999-01-21
PCT/JP2000/000278 WO2000043902A1 (en) 1999-01-21 2000-01-21 High-speed processor system, method of using the same, and recording medium

Publications (2)

Publication Number Publication Date
DE60010674D1 true DE60010674D1 (de) 2004-06-17
DE60010674T2 DE60010674T2 (de) 2005-06-16

Family

ID=11834461

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60010674T Expired - Lifetime DE60010674T2 (de) 1999-01-21 2000-01-21 Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium

Country Status (15)

Country Link
US (3) US6578110B1 (de)
EP (2) EP1161729B1 (de)
JP (1) JP3698358B2 (de)
KR (1) KR100678372B1 (de)
CN (1) CN100483389C (de)
AT (1) ATE266884T1 (de)
AU (1) AU3075600A (de)
BR (1) BR0008905A (de)
CA (1) CA2364338A1 (de)
DE (1) DE60010674T2 (de)
ES (1) ES2220386T3 (de)
HK (1) HK1039809A1 (de)
RU (1) RU2001122104A (de)
TW (1) TW472197B (de)
WO (1) WO2000043902A1 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0125711D0 (en) * 2001-10-26 2001-12-19 Ibm In-memory arithmetic
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US8392590B2 (en) * 2004-09-10 2013-03-05 Cavium, Inc. Deterministic finite automata (DFA) processing
US8301788B2 (en) * 2004-09-10 2012-10-30 Cavium, Inc. Deterministic finite automata (DFA) instruction
US8560475B2 (en) 2004-09-10 2013-10-15 Cavium, Inc. Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process
US20070005902A1 (en) * 2004-12-07 2007-01-04 Ocz Technology Group, Inc. Integrated sram cache for a memory module and method therefor
US7653785B2 (en) * 2005-06-22 2010-01-26 Lexmark International, Inc. Reconfigurable cache controller utilizing multiple ASIC SRAMS
US8819217B2 (en) * 2007-11-01 2014-08-26 Cavium, Inc. Intelligent graph walking
US8180803B2 (en) * 2007-11-27 2012-05-15 Cavium, Inc. Deterministic finite automata (DFA) graph compression
US7949683B2 (en) * 2007-11-27 2011-05-24 Cavium Networks, Inc. Method and apparatus for traversing a compressed deterministic finite automata (DFA) graph
JP2010015233A (ja) * 2008-07-01 2010-01-21 Panasonic Corp 集積回路及び電子機器
US8473523B2 (en) 2008-10-31 2013-06-25 Cavium, Inc. Deterministic finite automata graph traversal with nodal bit mapping
US9274950B2 (en) * 2009-08-26 2016-03-01 Hewlett Packard Enterprise Development Lp Data restructuring in multi-level memory hierarchies
US8331123B2 (en) * 2009-09-21 2012-12-11 Ocz Technology Group, Inc. High performance solid-state drives and methods therefor
US20130318269A1 (en) * 2012-05-22 2013-11-28 Xockets IP, LLC Processing structured and unstructured data using offload processors
KR102051816B1 (ko) * 2013-02-05 2019-12-04 에이알엠 리미티드 메모리 보호 유닛들을 사용한 가상화 지원 게스트 오퍼레이팅 시스템
JP6228523B2 (ja) * 2014-09-19 2017-11-08 東芝メモリ株式会社 メモリ制御回路および半導体記憶装置
CN105718380B (zh) * 2015-07-29 2019-06-04 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718995B (zh) * 2015-07-29 2019-02-01 上海磁宇信息科技有限公司 细胞阵列计算系统及其调试方法
CN105740946B (zh) * 2015-07-29 2019-02-12 上海磁宇信息科技有限公司 一种应用细胞阵列计算系统实现神经网络计算的方法
CN105608490B (zh) * 2015-07-29 2018-10-26 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105718994B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718991B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718992B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718993B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105718990B (zh) * 2015-07-29 2019-01-29 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中细胞之间的通信方法
CN105718996B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105718379B (zh) * 2015-07-29 2018-09-14 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中细胞间群发通信方法
CN105718392B (zh) * 2016-01-15 2019-01-29 上海磁宇信息科技有限公司 细胞阵列文件存储系统及其文件存储设备与文件存储方法
GB2542646B (en) * 2016-03-18 2017-11-15 Imagination Tech Ltd Non-linear cache logic
CN107291209B (zh) * 2016-04-01 2021-02-09 上海磁宇信息科技有限公司 细胞阵列计算系统
US10409754B2 (en) * 2016-04-28 2019-09-10 Smart Modular Technologies, Inc. Interconnected memory system and method of operation thereof
CN107341129B (zh) * 2016-04-29 2021-06-29 上海磁宇信息科技有限公司 细胞阵列计算系统及其测试方法
JP6493318B2 (ja) * 2016-06-24 2019-04-03 株式会社デンソー データ処理システム
GB2553102B (en) 2016-08-19 2020-05-20 Advanced Risc Mach Ltd A memory unit and method of operation of a memory unit to handle operation requests
KR102631380B1 (ko) * 2018-05-17 2024-02-01 에스케이하이닉스 주식회사 데이터 연산을 수행할 수 있는 다양한 메모리 장치를 포함하는 반도체 시스템

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2539385B2 (ja) * 1986-08-08 1996-10-02 株式会社日立製作所 情報処理装置
AU2278688A (en) 1988-02-16 1989-08-17 Sun Microsystems, Inc. Distributed cache architecture
JPH0239339A (ja) 1988-07-29 1990-02-08 Hitachi Ltd キヤツシユメモリ装置
EP0375883A3 (de) 1988-12-30 1991-05-29 International Business Machines Corporation Cache-Speicheranordnung
US5226169A (en) * 1988-12-30 1993-07-06 International Business Machines Corp. System for execution of storage-immediate and storage-storage instructions within cache buffer storage
JPH033047A (ja) 1989-05-31 1991-01-09 Nec Corp 演算機能付きメモリ
EP0446721B1 (de) * 1990-03-16 2000-12-20 Texas Instruments Incorporated Verteilter Verarbeitungsspeicher
US5617577A (en) * 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5260898A (en) 1992-03-13 1993-11-09 Sun Microsystems, Inc. Result cache for complex arithmetic units
KR940004434A (ko) * 1992-08-25 1994-03-15 윌리엄 이. 힐러 스마트 다이나믹 랜덤 억세스 메모리 및 그 처리방법
US6000027A (en) * 1992-08-25 1999-12-07 Texas Instruments Incorporated Method and apparatus for improved graphics/image processing using a processor and a memory
JP3207591B2 (ja) 1993-03-19 2001-09-10 株式会社日立製作所 キャッシュメモリを有する計算機の改良
US6226722B1 (en) * 1994-05-19 2001-05-01 International Business Machines Corporation Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing
DE19540915A1 (de) * 1994-11-10 1996-05-15 Raymond Engineering Redundante Anordnung von Festkörper-Speicherbausteinen
US5778436A (en) * 1995-03-06 1998-07-07 Duke University Predictive caching system and method based on memory access which previously followed a cache miss
US5900011A (en) 1996-07-01 1999-05-04 Sun Microsystems, Inc. Integrated processor/memory device with victim data cache
US5848254A (en) 1996-07-01 1998-12-08 Sun Microsystems, Inc. Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space
JP3075183B2 (ja) 1996-07-17 2000-08-07 日本電気株式会社 キャッシュメモリシステム
US5895487A (en) * 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
JPH10214223A (ja) 1997-01-29 1998-08-11 Hitachi Ltd 情報処理システム
US5987577A (en) * 1997-04-24 1999-11-16 International Business Machines Dual word enable method and apparatus for memory arrays
US6192451B1 (en) * 1998-02-17 2001-02-20 International Business Machines Corporation Cache coherency protocol for a data processing system including a multi-level memory hierarchy
US6453398B1 (en) * 1999-04-07 2002-09-17 Mitsubishi Electric Research Laboratories, Inc. Multiple access self-testing memory

Also Published As

Publication number Publication date
EP1161729A1 (de) 2001-12-12
WO2000043902A1 (en) 2000-07-27
DE60010674T2 (de) 2005-06-16
ES2220386T3 (es) 2004-12-16
HK1039809A1 (zh) 2002-05-10
CA2364338A1 (en) 2000-07-27
KR100678372B1 (ko) 2007-02-05
ATE266884T1 (de) 2004-05-15
JP3698358B2 (ja) 2005-09-21
CN1341242A (zh) 2002-03-20
US20030217228A1 (en) 2003-11-20
EP1161729B1 (de) 2004-05-12
EP1445701A2 (de) 2004-08-11
AU3075600A (en) 2000-08-07
US6745290B2 (en) 2004-06-01
KR20010101628A (ko) 2001-11-14
BR0008905A (pt) 2001-11-06
CN100483389C (zh) 2009-04-29
US7028141B2 (en) 2006-04-11
EP1445701A3 (de) 2009-03-25
JP2002535777A (ja) 2002-10-22
RU2001122104A (ru) 2003-06-27
TW472197B (en) 2002-01-11
US20040215881A1 (en) 2004-10-28
US6578110B1 (en) 2003-06-10

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