DE60013128D1 - Analoges verzögerungselement mit zwei ansteuereingängen - Google Patents

Analoges verzögerungselement mit zwei ansteuereingängen

Info

Publication number
DE60013128D1
DE60013128D1 DE60013128T DE60013128T DE60013128D1 DE 60013128 D1 DE60013128 D1 DE 60013128D1 DE 60013128 T DE60013128 T DE 60013128T DE 60013128 T DE60013128 T DE 60013128T DE 60013128 D1 DE60013128 D1 DE 60013128D1
Authority
DE
Germany
Prior art keywords
delay element
control inputs
analogue delay
analogue
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60013128T
Other languages
English (en)
Other versions
DE60013128T2 (de
Inventor
Ki-Jun Lee
Gurpreet Bhullar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of DE60013128D1 publication Critical patent/DE60013128D1/de
Application granted granted Critical
Publication of DE60013128T2 publication Critical patent/DE60013128T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—Dc control of switching transistors
DE2000613128 1999-02-26 2000-02-25 Analoges verzögerungselement mit zwei ansteuereingängen Expired - Lifetime DE60013128T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA 2263061 CA2263061C (en) 1999-02-26 1999-02-26 Dual control analog delay element
CA2263061 1999-02-26
PCT/CA2000/000202 WO2000052822A1 (en) 1999-02-26 2000-02-25 Dual control analog delay element

Publications (2)

Publication Number Publication Date
DE60013128D1 true DE60013128D1 (de) 2004-09-23
DE60013128T2 DE60013128T2 (de) 2005-09-01

Family

ID=4163333

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2000613128 Expired - Lifetime DE60013128T2 (de) 1999-02-26 2000-02-25 Analoges verzögerungselement mit zwei ansteuereingängen

Country Status (8)

Country Link
US (3) US6559699B2 (de)
EP (1) EP1188239B1 (de)
JP (1) JP4590106B2 (de)
KR (1) KR100690442B1 (de)
AU (1) AU2790100A (de)
CA (1) CA2263061C (de)
DE (1) DE60013128T2 (de)
WO (1) WO2000052822A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2263061C (en) * 1999-02-26 2011-01-25 Ki-Jun Lee Dual control analog delay element
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
US7138845B2 (en) * 2004-07-22 2006-11-21 Micron Technology, Inc. Method and apparatus to set a tuning range for an analog delay
KR100888483B1 (ko) * 2007-05-16 2009-03-12 삼성전자주식회사 공정 변동을 보상하는 기준 바이어스 회로
TWI400592B (zh) * 2009-09-15 2013-07-01 Acer Inc 線性穩壓器
JP2011114773A (ja) * 2009-11-30 2011-06-09 Elpida Memory Inc 半導体装置、半導体装置の制御方法及び該半導体装置を用いたシステム
US7982516B1 (en) 2010-03-19 2011-07-19 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. RC-based delay element and method for reducing frequency induced delay variation
US11206838B2 (en) 2013-04-11 2021-12-28 General Mills, Inc. Batter compositions, packaged batter products, and related methods
KR20150037034A (ko) 2013-09-30 2015-04-08 에스케이하이닉스 주식회사 반도체 장치
US10236871B2 (en) * 2016-10-28 2019-03-19 Mosway Technologies Limited Pulse width filtering circuit
CN107968649B (zh) * 2017-11-13 2021-01-12 东南大学 一种高精度数字时间转换器及其控制方法
CN110011652B (zh) * 2019-04-08 2024-04-02 北京承力电源有限公司 一种开关电源至少二级启动时序控制电路

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JPS58184817A (ja) * 1982-02-26 1983-10-28 Yokogawa Hewlett Packard Ltd 遅延回路
JPS60103822A (ja) * 1983-11-11 1985-06-08 Hitachi Ltd 遅延回路
US4633152A (en) * 1984-11-29 1986-12-30 Abex Corporation Direct current motor controller
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
JPH03283912A (ja) * 1990-03-30 1991-12-13 Advantest Corp 可変遅延回路
US5355391A (en) * 1992-03-06 1994-10-11 Rambus, Inc. High speed bus system
US5650739A (en) * 1992-12-07 1997-07-22 Dallas Semiconductor Corporation Programmable delay lines
US5570243A (en) * 1993-06-22 1996-10-29 Fujitsu Limited Variable delay circuit including current mirror and ramp generator circuits for use in the read channel of a data storage device
JPH0795022A (ja) * 1993-09-22 1995-04-07 Toshiba Corp 遅延回路
JPH07202656A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 遅延回路装置
US5495161A (en) * 1994-01-05 1996-02-27 Sencorp Speed control for a universal AC/DC motor
US5440515A (en) * 1994-03-08 1995-08-08 Motorola Inc. Delay locked loop for detecting the phase difference of two signals having different frequencies
JP3553639B2 (ja) * 1994-05-12 2004-08-11 アジレント・テクノロジーズ・インク タイミング調整回路
JPH08125509A (ja) * 1994-10-25 1996-05-17 Mitsubishi Electric Corp 可変遅延回路、リング発振器、及びフリップフロップ回路
JP3109560B2 (ja) * 1995-02-10 2000-11-20 日本電気株式会社 ばらつき補償技術による半導体集積回路
JPH08222966A (ja) * 1995-02-14 1996-08-30 Nec Corp サンプル・ホールド回路
JP3702038B2 (ja) * 1996-05-14 2005-10-05 株式会社ルネサステクノロジ 遅延回路
KR100214510B1 (ko) * 1996-10-15 1999-08-02 구본준 센스앰프의 전력 차단 회로
JP3732914B2 (ja) * 1997-02-28 2006-01-11 株式会社ルネサステクノロジ 半導体装置
US5852360A (en) * 1997-04-18 1998-12-22 Exar Corporation Programmable low drift reference voltage generator
US6101106A (en) * 1999-02-05 2000-08-08 The Boeing Company Pulse width modulated controller for high temperature power conversion
CA2263061C (en) * 1999-02-26 2011-01-25 Ki-Jun Lee Dual control analog delay element
US6870415B2 (en) * 2002-09-12 2005-03-22 Broadcom Corporation Delay generator with controlled delay circuit
JP4076079B2 (ja) * 2003-01-08 2008-04-16 株式会社日立製作所 半導体集積回路装置および半導体集積回路
WO2004102805A1 (ja) * 2003-05-13 2004-11-25 Fujitsu Limited 遅延回路
JP3732841B2 (ja) * 2003-07-04 2006-01-11 株式会社東芝 遅延回路
US7064587B2 (en) * 2003-11-28 2006-06-20 Texas Instruments Incorporated Output Buffer
US7391257B1 (en) * 2007-01-31 2008-06-24 Medtronic, Inc. Chopper-stabilized instrumentation amplifier for impedance measurement

Also Published As

Publication number Publication date
JP4590106B2 (ja) 2010-12-01
US20030231041A1 (en) 2003-12-18
AU2790100A (en) 2000-09-21
JP2003533900A (ja) 2003-11-11
US6559699B2 (en) 2003-05-06
CA2263061C (en) 2011-01-25
US7263117B2 (en) 2007-08-28
WO2000052822A1 (en) 2000-09-08
EP1188239A1 (de) 2002-03-20
US20020027464A1 (en) 2002-03-07
KR100690442B1 (ko) 2007-03-09
EP1188239B1 (de) 2004-08-18
US20080036500A1 (en) 2008-02-14
US8063687B2 (en) 2011-11-22
CA2263061A1 (en) 2000-08-26
DE60013128T2 (de) 2005-09-01
KR20010112287A (ko) 2001-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA