DE60018101D1 - Testmuster-kompression für eine testumgebung von integrierten schaltungen - Google Patents
Testmuster-kompression für eine testumgebung von integrierten schaltungenInfo
- Publication number
- DE60018101D1 DE60018101D1 DE60018101T DE60018101T DE60018101D1 DE 60018101 D1 DE60018101 D1 DE 60018101D1 DE 60018101 T DE60018101 T DE 60018101T DE 60018101 T DE60018101 T DE 60018101T DE 60018101 D1 DE60018101 D1 DE 60018101D1
- Authority
- DE
- Germany
- Prior art keywords
- test
- scan
- symbolic expressions
- symbolic
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16744699P | 1999-11-23 | 1999-11-23 | |
| US167446P | 1999-11-23 | ||
| US619985 | 2000-07-20 | ||
| US09/619,985 US6327687B1 (en) | 1999-11-23 | 2000-07-20 | Test pattern compression for an integrated circuit test environment |
| PCT/US2000/031377 WO2001038981A1 (en) | 1999-11-23 | 2000-11-15 | Test pattern compression for an integrated circuit test environment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60018101D1 true DE60018101D1 (de) | 2005-03-17 |
| DE60018101T2 DE60018101T2 (de) | 2006-01-12 |
Family
ID=26863184
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60018101T Expired - Lifetime DE60018101T2 (de) | 1999-11-23 | 2000-11-15 | Testmuster-kompression für eine testumgebung von integrierten schaltungen |
| DE60030896T Expired - Lifetime DE60030896T2 (de) | 1999-11-23 | 2000-11-15 | Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60030896T Expired - Lifetime DE60030896T2 (de) | 1999-11-23 | 2000-11-15 | Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen |
Country Status (7)
| Country | Link |
|---|---|
| US (5) | US6327687B1 (de) |
| EP (1) | EP1236111B1 (de) |
| JP (1) | JP3920640B2 (de) |
| AT (2) | ATE340363T1 (de) |
| DE (2) | DE60018101T2 (de) |
| HK (1) | HK1049215A1 (de) |
| WO (1) | WO2001038981A1 (de) |
Families Citing this family (131)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661839B1 (en) * | 1998-03-24 | 2003-12-09 | Advantest Corporation | Method and device for compressing and expanding data pattern |
| US7417450B2 (en) * | 2005-12-02 | 2008-08-26 | Texas Instruments Incorporated | Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit |
| US7493540B1 (en) * | 1999-11-23 | 2009-02-17 | Jansuz Rajski | Continuous application and decompression of test patterns to a circuit-under-test |
| US9664739B2 (en) | 1999-11-23 | 2017-05-30 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
| US6327687B1 (en) * | 1999-11-23 | 2001-12-04 | Janusz Rajski | Test pattern compression for an integrated circuit test environment |
| WO2001039254A2 (en) | 1999-11-23 | 2001-05-31 | Mentor Graphics Corporation | Continuous application and decompression of test patterns to a circuit-under-test |
| US6684358B1 (en) | 1999-11-23 | 2004-01-27 | Janusz Rajski | Decompressor/PRPG for applying pseudo-random and deterministic test patterns |
| US6874109B1 (en) | 1999-11-23 | 2005-03-29 | Janusz Rajski | Phase shifter with reduced linear dependency |
| US6557129B1 (en) * | 1999-11-23 | 2003-04-29 | Janusz Rajski | Method and apparatus for selectively compacting test responses |
| US8533547B2 (en) | 1999-11-23 | 2013-09-10 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
| US9134370B2 (en) | 1999-11-23 | 2015-09-15 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
| US6353842B1 (en) | 1999-11-23 | 2002-03-05 | Janusz Rajski | Method for synthesizing linear finite state machines |
| US6615380B1 (en) * | 1999-12-21 | 2003-09-02 | Synopsys Inc. | Dynamic scan chains and test pattern generation methodologies therefor |
| DE60108993T2 (de) | 2000-03-09 | 2005-07-21 | Texas Instruments Inc., Dallas | Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch |
| US6611933B1 (en) * | 2000-04-12 | 2003-08-26 | International Business Machines Corporation | Real-time decoder for scan test patterns |
| US6658617B1 (en) | 2000-05-11 | 2003-12-02 | Fujitsu Limited | Handling a 1-hot multiplexer during built-in self-testing of logic |
| US6865706B1 (en) * | 2000-06-07 | 2005-03-08 | Agilent Technologies, Inc. | Apparatus and method for generating a set of test vectors using nonrandom filling |
| US6411228B1 (en) * | 2000-09-21 | 2002-06-25 | International Business Machines Corporation | Apparatus and method for compressing pseudo-random data using distribution approximations |
| US6636997B1 (en) * | 2000-10-24 | 2003-10-21 | Fujitsu Limited | System and method for improving LBIST test coverage |
| US6618841B1 (en) * | 2000-11-06 | 2003-09-09 | Verplex Systems, Inc. | Non-assignable signal support during formal verification of circuit designs |
| US6715105B1 (en) * | 2000-11-14 | 2004-03-30 | Agilent Technologies, Inc. | Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port |
| JP4228061B2 (ja) * | 2000-12-07 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 集積回路の試験装置および試験方法 |
| JP3937034B2 (ja) * | 2000-12-13 | 2007-06-27 | 株式会社日立製作所 | 半導体集積回路のテスト方法及びテストパターン発生回路 |
| US6782501B2 (en) * | 2001-01-23 | 2004-08-24 | Cadence Design Systems, Inc. | System for reducing test data volume in the testing of logic products |
| US7103816B2 (en) * | 2001-01-23 | 2006-09-05 | Cadence Design Systems, Inc. | Method and system for reducing test data volume in the testing of logic products |
| US6732312B2 (en) * | 2001-03-09 | 2004-05-04 | Agilent Technologies, Inc. | Test vector compression method |
| US6950974B1 (en) * | 2001-09-07 | 2005-09-27 | Synopsys Inc. | Efficient compression and application of deterministic patterns in a logic BIST architecture |
| US7412637B2 (en) * | 2003-01-10 | 2008-08-12 | Syntest Technologies, Inc. | Method and apparatus for broadcasting test patterns in a scan based integrated circuit |
| US7412672B1 (en) | 2002-01-16 | 2008-08-12 | Syntest Technologies, Inc. | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit |
| US9062710B2 (en) | 2013-02-05 | 2015-06-23 | Schaeffler Technologies AG & Co. KG | Combined load rolling bearing |
| US7552373B2 (en) | 2002-01-16 | 2009-06-23 | Syntest Technologies, Inc. | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit |
| US7185253B2 (en) * | 2002-03-27 | 2007-02-27 | Intel Corporation | Compacting circuit responses |
| US7444567B2 (en) * | 2002-04-09 | 2008-10-28 | Syntest Technologies, Inc. | Method and apparatus for unifying self-test with scan-test during prototype debug and production test |
| US7234092B2 (en) * | 2002-06-11 | 2007-06-19 | On-Chip Technologies, Inc. | Variable clocked scan test circuitry and method |
| EP1382975B1 (de) * | 2002-07-19 | 2008-01-02 | Qimonda AG | Verfahren zur Erzeugung eines Testmusters für die Simulation und/oder Prüfung des Layouts einer integrierten Schaltung |
| US20040153926A1 (en) * | 2002-10-30 | 2004-08-05 | Abdel-Hafez Khader S. | Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit |
| US7424417B2 (en) * | 2002-11-19 | 2008-09-09 | Broadcom Corporation | System and method for clock domain grouping using data path relationships |
| US7240260B2 (en) * | 2002-12-11 | 2007-07-03 | Intel Corporation | Stimulus generation |
| US7197721B2 (en) * | 2002-12-17 | 2007-03-27 | Intel Corporation | Weight compression/decompression system |
| US7721173B2 (en) * | 2003-01-10 | 2010-05-18 | Syntest Technologies, Inc. | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit |
| US7200784B2 (en) * | 2003-01-24 | 2007-04-03 | On-Chip Technologies, Inc. | Accelerated scan circuitry and method for reducing scan test data volume and execution time |
| US7302624B2 (en) * | 2003-02-13 | 2007-11-27 | Janusz Rajski | Adaptive fault diagnosis of compressed test responses |
| JP4791954B2 (ja) * | 2003-02-13 | 2011-10-12 | メンター・グラフィクス・コーポレーション | コンパクタを使用する試験応答の圧縮 |
| US7437640B2 (en) * | 2003-02-13 | 2008-10-14 | Janusz Rajski | Fault diagnosis of compressed test responses having one or more unknown states |
| US7509550B2 (en) * | 2003-02-13 | 2009-03-24 | Janusz Rajski | Fault diagnosis of compressed test responses |
| US7219280B2 (en) * | 2003-02-24 | 2007-05-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated circuit with test signal routing module |
| US7584392B2 (en) * | 2003-05-23 | 2009-09-01 | Cadence Design Systems, Inc. | Test compaction using linear-matrix driven scan chains |
| US7240268B2 (en) * | 2003-05-30 | 2007-07-03 | Arm Limited | Test component and method of operation thereof |
| US7404109B2 (en) * | 2003-06-12 | 2008-07-22 | Verigy (Singapore) Pte. Ltd. | Systems and methods for adaptively compressing test data |
| US7512851B2 (en) * | 2003-08-01 | 2009-03-31 | Syntest Technologies, Inc. | Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit |
| US7523370B1 (en) | 2003-09-15 | 2009-04-21 | Cadence Design Systems, Inc. | Channel masking during integrated circuit testing |
| US7278123B2 (en) * | 2003-10-17 | 2007-10-02 | Nec Laboratories America, Inc. | System-level test architecture for delivery of compressed tests |
| US7657809B1 (en) | 2003-11-19 | 2010-02-02 | Cadence Design Systems, Inc. | Dual scan chain design method and apparatus |
| US7055118B1 (en) | 2004-03-01 | 2006-05-30 | Sun Microsystems, Inc. | Scan chain verification using symbolic simulation |
| US7239978B2 (en) * | 2004-03-31 | 2007-07-03 | Wu-Tung Cheng | Compactor independent fault diagnosis |
| US8280687B2 (en) * | 2004-03-31 | 2012-10-02 | Mentor Graphics Corporation | Direct fault diagnostics using per-pattern compactor signatures |
| US7729884B2 (en) * | 2004-03-31 | 2010-06-01 | Yu Huang | Compactor independent direct diagnosis of test hardware |
| US7386777B2 (en) * | 2004-04-05 | 2008-06-10 | Verigy (Singapore) Pte. Ltd. | Systems and methods for processing automatically generated test patterns |
| US7945833B1 (en) | 2004-05-24 | 2011-05-17 | Syntest Technologies, Inc. | Method and apparatus for pipelined scan compression |
| US7590905B2 (en) * | 2004-05-24 | 2009-09-15 | Syntest Technologies, Inc. | Method and apparatus for pipelined scan compression |
| US7231570B2 (en) * | 2004-05-26 | 2007-06-12 | Syntest Technologies, Inc. | Method and apparatus for multi-level scan compression |
| US7418640B2 (en) * | 2004-05-28 | 2008-08-26 | Synopsys, Inc. | Dynamically reconfigurable shared scan-in test architecture |
| JP4733935B2 (ja) * | 2004-06-29 | 2011-07-27 | 富士通セミコンダクター株式会社 | 試験パターン生成装置、テスト回路試験装置、試験パターン生成方法、テスト回路試験方法、試験パターン生成プログラム、テスト回路試験プログラム、および記録媒体 |
| US7500165B2 (en) | 2004-10-06 | 2009-03-03 | Broadcom Corporation | Systems and methods for controlling clock signals during scan testing integrated circuits |
| US7353470B2 (en) * | 2005-02-14 | 2008-04-01 | On-Chip Technologies, Inc. | Variable clocked scan test improvements |
| US7487420B2 (en) * | 2005-02-15 | 2009-02-03 | Cadence Design Systems Inc. | System and method for performing logic failure diagnosis using multiple input signature register output streams |
| US8117513B2 (en) * | 2005-03-30 | 2012-02-14 | Lptex Corporation | Test method and test program of semiconductor logic circuit device |
| KR101010504B1 (ko) | 2005-07-26 | 2011-01-21 | 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 | 반도체 논리회로장치의 테스트벡터 생성 방법 및테스트벡터 생성 프로그램 |
| US7412636B2 (en) * | 2005-08-23 | 2008-08-12 | Oc Applications Research Llc | Scan string segmentation for digital test compression |
| US7363603B2 (en) * | 2005-09-13 | 2008-04-22 | International Business Machines Corporation | Method and system for case-splitting on nodes in a symbolic simulation framework |
| US7484151B2 (en) * | 2005-10-03 | 2009-01-27 | Nec Laboratories America, Inc. | Method and apparatus for testing logic circuit designs |
| US7415678B2 (en) * | 2005-11-15 | 2008-08-19 | Synopsys, Inc. | Method and apparatus for synthesis of multimode X-tolerant compressor |
| EP2677328B1 (de) | 2006-02-17 | 2015-07-29 | Mentor Graphics Corporation | Mehrstufige Testreaktionsverdichter |
| US20070266283A1 (en) * | 2006-05-01 | 2007-11-15 | Nec Laboratories America, Inc. | Method and Apparatus for Testing an Integrated Circuit |
| EP1852706B1 (de) * | 2006-05-04 | 2009-10-28 | STMicroelectronics S.r.l. | Adaptive Scan-compression Architektur |
| JP4482622B2 (ja) * | 2006-06-30 | 2010-06-16 | 独立行政法人科学技術振興機構 | 変換装置、変換方法、変換方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体 |
| US7647540B2 (en) | 2006-07-21 | 2010-01-12 | Janusz Rajski | Decompressors for low power decompression of test patterns |
| US7797603B2 (en) * | 2006-07-21 | 2010-09-14 | Janusz Rajski | Low power decompression of test cubes |
| TWI312075B (en) * | 2006-11-30 | 2009-07-11 | Ind Tech Res Inst | Scan test data compression method and decoding apparatus for multiple-scan-chain designs |
| WO2008096922A1 (en) * | 2007-02-09 | 2008-08-14 | Industry-Academic Cooperation Foundation, Yonsei University | Method for diagnosing troubles in scan chain via symbolic simulation |
| CN101663648B (zh) | 2007-02-12 | 2012-10-03 | 明导公司 | 低功耗扫描测试技术及装置 |
| US20080208752A1 (en) * | 2007-02-23 | 2008-08-28 | Microsoft Corporation | Content communication and purchase using a computer-based media component |
| US7877712B2 (en) * | 2007-05-07 | 2011-01-25 | International Business Machines Corporation | System for and method of verifying IC authenticity |
| US7739635B2 (en) * | 2007-05-10 | 2010-06-15 | International Business Machines Corporation | Conjunctive BDD building and variable quantification using case-splitting |
| US7673204B2 (en) * | 2007-07-05 | 2010-03-02 | International Business Machines Corporation | Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit |
| US7882409B2 (en) * | 2007-09-21 | 2011-02-01 | Synopsys, Inc. | Method and apparatus for synthesis of augmented multimode compactors |
| US7949921B2 (en) * | 2007-09-21 | 2011-05-24 | Synopsys, Inc. | Method and apparatus for synthesis of augmented multimode compactors |
| US7831876B2 (en) * | 2007-10-23 | 2010-11-09 | Lsi Corporation | Testing a circuit with compressed scan chain subsets |
| US8584073B2 (en) | 2008-07-21 | 2013-11-12 | Synopsys, Inc. | Test design optimizer for configurable scan architectures |
| TWI403746B (zh) * | 2008-10-22 | 2013-08-01 | 國立臺灣大學 | 測試圖案最佳化的方法 |
| US8006152B2 (en) * | 2009-01-12 | 2011-08-23 | International Business Machines Corporation | Scan chain fail diagnostics |
| US8214170B2 (en) | 2009-01-15 | 2012-07-03 | International Business Machines Corporation | Test pattern compression |
| US8499209B2 (en) * | 2009-04-22 | 2013-07-30 | Mentor Graphics Corporation | At-speed scan testing with controlled switching activity |
| US20110022907A1 (en) * | 2009-06-23 | 2011-01-27 | StarDFX Technologies, Inc. | FPGA Test Configuration Minimization |
| US7996741B2 (en) | 2009-08-24 | 2011-08-09 | Syntest Technologies, Inc. | Method and apparatus for low-pin-count scan compression |
| US10955460B2 (en) * | 2010-03-16 | 2021-03-23 | Mentor Graphics Corporation | Test scheduling and test access in test compression environment |
| US8433961B2 (en) * | 2010-05-06 | 2013-04-30 | Arm Limited | Data processing apparatus and method for testing a circuit block using scan chains |
| JP5408052B2 (ja) * | 2010-06-23 | 2014-02-05 | 富士通セミコンダクター株式会社 | 集積回路、シミュレーション装置、及びシミュレーション方法 |
| US8468404B1 (en) * | 2010-06-25 | 2013-06-18 | Cadence Design Systems, Inc. | Method and system for reducing switching activity during scan-load operations |
| US8473792B2 (en) * | 2011-01-06 | 2013-06-25 | Lsi Corporation | Logic BIST for system testing using stored patterns |
| KR20140002914A (ko) * | 2012-06-28 | 2014-01-09 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 테스트 회로 및 이를 포함하는 반도체 메모리 시스템 |
| US10345369B2 (en) | 2012-10-02 | 2019-07-09 | Synopsys, Inc. | Augmented power-aware decompressor |
| US8839063B2 (en) * | 2013-01-24 | 2014-09-16 | Texas Instruments Incorporated | Circuits and methods for dynamic allocation of scan test resources |
| US9335377B2 (en) | 2013-06-17 | 2016-05-10 | Mentor Graphics Corporation | Test-per-clock based on dynamically-partitioned reconfigurable scan chains |
| US9347993B2 (en) * | 2013-06-17 | 2016-05-24 | Mentor Graphics Corporation | Test generation for test-per-clock |
| US10379161B2 (en) | 2013-06-17 | 2019-08-13 | Mentor Graphics Corporation | Scan chain stitching for test-per-clock |
| US9003248B2 (en) * | 2013-06-17 | 2015-04-07 | Mentor Graphics Corporation | Fault-driven scan chain configuration for test-per-clock |
| US9915702B2 (en) * | 2013-11-26 | 2018-03-13 | Mentor Graphics Corporation | Channel sharing for testing circuits having non-identical cores |
| US9864007B2 (en) | 2014-04-30 | 2018-01-09 | Duke University | Software-based self-test and diagnosis using on-chip memory |
| US9519026B2 (en) | 2014-09-30 | 2016-12-13 | Apple Inc. | Compressed scan testing techniques |
| US10215803B1 (en) | 2014-10-15 | 2019-02-26 | Santiago Remersaro | Method and apparatus for concurrent inter-test response compaction and diagnosis |
| TW201809712A (zh) * | 2014-10-29 | 2018-03-16 | 因諾帝歐股份有限公司 | 積體電路晶片測試裝置，方法及系統 |
| US9933485B2 (en) | 2015-02-24 | 2018-04-03 | Mentor Graphics Corporation | Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives |
| US10380303B2 (en) | 2015-11-30 | 2019-08-13 | Synopsys, Inc. | Power-aware dynamic encoding |
| US10180457B1 (en) * | 2016-03-04 | 2019-01-15 | Cadence Design Systems, Inc. | System and method performing scan chain diagnosis of an electronic design |
| CN106354692B (zh) * | 2016-08-30 | 2019-05-03 | 工业和信息化部电子第五研究所 | 面向SoC的片上TDDB退化监测及失效预警电路 |
| TWI612317B (zh) * | 2016-11-01 | 2018-01-21 | 國立成功大學 | 一種測試資料之解壓縮器及其測試方法 |
| US11143697B2 (en) * | 2017-04-28 | 2021-10-12 | Advantest Corporation | Automated handling of different form factor devices under test in test cell |
| US11422188B2 (en) | 2018-03-22 | 2022-08-23 | Siemens Industry Software Inc | Isometric control data generation for test compression |
| US10996273B2 (en) | 2018-03-22 | 2021-05-04 | Siemens Industry Software Inc. | Test generation using testability-based guidance |
| EP3756021A1 (de) | 2018-03-22 | 2020-12-30 | Mentor Graphics Corporation | Flexible isometrische dekompressorarchitektur für testkompression |
| WO2019183296A1 (en) | 2018-03-22 | 2019-09-26 | Mentor Graphics Corporation | Deterministic stellar built-in self-test |
| US10678667B1 (en) * | 2018-12-21 | 2020-06-09 | Micron Technology, Inc. | Holdup self-tests for power loss operations on memory systems |
| US10746790B1 (en) * | 2019-03-25 | 2020-08-18 | International Business Machines Corporation | Constrained pseudorandom test pattern for in-system logic built-in self-test |
| US11073557B2 (en) * | 2019-05-08 | 2021-07-27 | Texas Instruments Incorporated | Phase controlled codec block scan of a partitioned circuit device |
| US11815555B2 (en) | 2019-09-06 | 2023-11-14 | Siemens Industry Software Inc. | Universal compactor architecture for testing circuits |
| KR20210047127A (ko) | 2019-10-21 | 2021-04-29 | 삼성전자주식회사 | 반도체 회로를 검증하기 위한 최적화된 검증 벡터를 생성하는 전자 장치 및 그 동작 방법 |
| US11232246B2 (en) | 2019-11-14 | 2022-01-25 | Siemens Industry Software Inc. | Layout-friendly test pattern decompressor |
| US11106848B2 (en) | 2019-11-14 | 2021-08-31 | Siemens Industry Software Inc. | Diagnostic resolution enhancement with reversible scan chains |
| WO2023107096A1 (en) | 2021-12-07 | 2023-06-15 | Siemens Industry Software Inc. | X-masking for in-system deterministic test |
| US20240085471A1 (en) * | 2022-09-09 | 2024-03-14 | Infineon Technologies Ag | Test arrangement and method for testing an integrated circuit |
Family Cites Families (140)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US519078A (en) * | 1894-05-01 | Martin middleton wilson | ||
| US124217A (en) * | 1872-03-05 | Improvement in seal-locks | ||
| US112199A (en) * | 1871-02-28 | Improvement in fire-places | ||
| US713605A (en) * | 1899-11-13 | 1902-11-18 | Gen Electric | Transformer. |
| US3614400A (en) | 1969-11-26 | 1971-10-19 | Rca Corp | Maximum length pulse sequence generators |
| US3700869A (en) | 1970-12-04 | 1972-10-24 | Nasa | Pseudonoise sequence generators with three-tap linear feedback shift registers |
| US4024460A (en) * | 1973-11-23 | 1977-05-17 | Hewlett-Packard Company | Electronic line stretcher |
| US4122399A (en) * | 1977-12-07 | 1978-10-24 | Bell Telephone Laboratories, Incorporated | Distortion generator |
| US4161041A (en) | 1978-10-06 | 1979-07-10 | The United States Of America As Represented By The Secretary Of The Air Force | Pseudo random number generator apparatus |
| GB2049958B (en) | 1979-03-15 | 1983-11-30 | Nippon Electric Co | Integrated logic circuit adapted to performance tests |
| US4320509A (en) | 1979-10-19 | 1982-03-16 | Bell Telephone Laboratories, Incorporated | LSI Circuit logic structure including data compression circuitry |
| US4513418A (en) | 1982-11-08 | 1985-04-23 | International Business Machines Corporation | Simultaneous self-testing system |
| US4503537A (en) | 1982-11-08 | 1985-03-05 | International Business Machines Corporation | Parallel path self-testing system |
| US5974433A (en) | 1984-06-29 | 1999-10-26 | Currie; Robert John | High speed M-sequence generator and decoder circuit |
| US4602210A (en) * | 1984-12-28 | 1986-07-22 | General Electric Company | Multiplexed-access scan testable integrated circuit |
| US4785410A (en) | 1985-06-05 | 1988-11-15 | Clarion Co., Ltd. | Maximum length shift register sequences generator |
| US4687988A (en) | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
| US4801870A (en) | 1985-06-24 | 1989-01-31 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
| US4754215A (en) | 1985-11-06 | 1988-06-28 | Nec Corporation | Self-diagnosable integrated circuit device capable of testing sequential circuit elements |
| JP2628154B2 (ja) | 1986-12-17 | 1997-07-09 | 富士通株式会社 | 半導体集積回路 |
| US4827476A (en) * | 1987-04-16 | 1989-05-02 | Tandem Computers Incorporated | Scan test apparatus for digital systems having dynamic random access memory |
| US4860236A (en) | 1987-10-26 | 1989-08-22 | University Of Manitoba | Cellular automaton for generating random data |
| JPH01132979A (ja) * | 1987-11-17 | 1989-05-25 | Mitsubishi Electric Corp | テスト機能付電子回路 |
| JPH01239486A (ja) | 1988-03-18 | 1989-09-25 | Nec Corp | 出力応答圧縮器 |
| US4974184A (en) | 1988-05-05 | 1990-11-27 | Honeywell Inc. | Maximum length pseudo-random test pattern generator via feedback network modification |
| EP0350538B1 (de) | 1988-07-13 | 1993-12-01 | Koninklijke Philips Electronics N.V. | Speichergerät, das einen zur Ausführung einer Selbstprüfung adaptierten statischen RAM-Speicher enthält und integrierte Schaltung, die als eingebauten statischen RAM-Speicher ein solches Gerät enthält |
| US4959832A (en) | 1988-12-09 | 1990-09-25 | International Business Machines | Parallel pseudorandom pattern generator with varying phase shift |
| JP2591825B2 (ja) | 1989-05-30 | 1997-03-19 | 富士通株式会社 | 圧縮データを用いた論理回路試験方法及びその装置 |
| JP2584673B2 (ja) | 1989-06-09 | 1997-02-26 | 株式会社日立製作所 | テストデータ変更回路を有する論理回路テスト装置 |
| JPH03214809A (ja) | 1990-01-19 | 1991-09-20 | Nec Corp | リニアフィードバック・シフトレジスタ |
| US5138619A (en) | 1990-02-15 | 1992-08-11 | National Semiconductor Corporation | Built-in self test for integrated circuit memory |
| US5268949A (en) | 1990-03-28 | 1993-12-07 | Ando Electric Co., Ltd. | Circuit for generating M-sequence pseudo-random pattern |
| IL94115A (en) * | 1990-04-18 | 1996-06-18 | Ibm Israel | Dynamic process for creating pseudo-random test templates for pompous hardware design violence |
| EP0460352B1 (de) * | 1990-06-07 | 1995-11-02 | International Business Machines Corporation | System zur Reduzierung von Prüfdatenspeichern |
| US5167034A (en) * | 1990-06-18 | 1992-11-24 | International Business Machines Corporation | Data integrity for compaction devices |
| US5173906A (en) | 1990-08-31 | 1992-12-22 | Dreibelbis Jeffrey H | Built-in self test for integrated circuits |
| EP0481097B1 (de) | 1990-09-15 | 1995-06-14 | International Business Machines Corporation | Procédé et appareil pour tester des circuits intégrés à grande integration |
| US5258986A (en) * | 1990-09-19 | 1993-11-02 | Vlsi Technology, Inc. | Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories |
| US5293123A (en) * | 1990-10-19 | 1994-03-08 | Tandem Computers Incorporated | Pseudo-Random scan test apparatus |
| JP2584172B2 (ja) | 1991-08-23 | 1997-02-19 | インターナショナル・ビジネス・マシーンズ・コーポレイション | デイジタル試験信号発生回路 |
| US5369648A (en) | 1991-11-08 | 1994-11-29 | Ncr Corporation | Built-in self-test circuit |
| JPH05215816A (ja) | 1991-12-06 | 1993-08-27 | Nec Corp | 情報処理装置 |
| EP0549949B1 (de) | 1991-12-16 | 1998-03-11 | Nippon Telegraph And Telephone Corporation | Schaltung mit eingebautem Selbsttest |
| US5412665A (en) | 1992-01-10 | 1995-05-02 | International Business Machines Corporation | Parallel operation linear feedback shift register |
| US5349587A (en) * | 1992-03-26 | 1994-09-20 | Northern Telecom Limited | Multiple clock rate test apparatus for testing digital systems |
| US5394405A (en) | 1992-04-24 | 1995-02-28 | International Business Machines Corporation | Universal weight generator |
| JP3474214B2 (ja) * | 1992-10-22 | 2003-12-08 | 株式会社東芝 | 論理回路及びこの論理回路を備えたテスト容易化回路 |
| US5608870A (en) | 1992-11-06 | 1997-03-04 | The President And Fellows Of Harvard College | System for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target address |
| US5701309A (en) * | 1992-12-02 | 1997-12-23 | At&T Global Information Solutions Company | Automated test equipment digital tester expansion apparatus |
| US5586125A (en) | 1993-02-26 | 1996-12-17 | Warner; William T. | Method for generating test vectors for characterizing and verifying the operation of integrated circuits |
| EP0620518B1 (de) | 1993-04-06 | 1999-10-06 | Hewlett-Packard Company | Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen |
| US5450414A (en) | 1993-05-17 | 1995-09-12 | At&T Corp. | Partial-scan built-in self-testing circuit having improved testability |
| US5416783A (en) * | 1993-08-09 | 1995-05-16 | Motorola, Inc. | Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor |
| US5444716A (en) * | 1993-08-30 | 1995-08-22 | At&T Corp. | Boundary-scan-based system and method for test and diagnosis |
| US5414716A (en) | 1993-09-22 | 1995-05-09 | Mitsubishi Electronic Research Laboratories, Inc. | Weighting system for testing of circuits utilizing determination of undetected faults |
| US5848198A (en) | 1993-10-08 | 1998-12-08 | Penn; Alan Irvin | Method of and apparatus for analyzing images and deriving binary image representations |
| US5524114A (en) * | 1993-10-22 | 1996-06-04 | Lsi Logic Corporation | Method and apparatus for testing semiconductor devices at speed |
| US5617531A (en) * | 1993-11-02 | 1997-04-01 | Motorola, Inc. | Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor |
| US5631913A (en) | 1994-02-09 | 1997-05-20 | Matsushita Electric Industrial Co., Ltd. | Test circuit and test method of integrated semiconductor device |
| US5694401A (en) * | 1994-06-27 | 1997-12-02 | Tandem Computers Incorporated | Fault isolation using pseudo-random scan |
| US6029263A (en) * | 1994-06-30 | 2000-02-22 | Tandem Computers Incorporated | Interconnect testing using non-compatible scan architectures |
| US5642362A (en) | 1994-07-20 | 1997-06-24 | International Business Machines Corporation | Scan-based delay tests having enhanced test vector pattern generation |
| US5592493A (en) | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
| US5748497A (en) | 1994-10-31 | 1998-05-05 | Texas Instruments Incorporated | System and method for improving fault coverage of an electric circuit |
| US5533128A (en) | 1995-01-18 | 1996-07-02 | Vobach; Arnold | Pseudo-random transposition cipher system and method |
| US5974179A (en) * | 1995-02-13 | 1999-10-26 | Integrated Device Technology, Inc. | Binary image data compression and decompression |
| US5717702A (en) * | 1995-03-14 | 1998-02-10 | Hughes Electronics | Scan testing digital logic with differing frequencies of system clock and test clock |
| US5761489A (en) * | 1995-04-17 | 1998-06-02 | Motorola Inc. | Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system |
| US5553082A (en) * | 1995-05-01 | 1996-09-03 | International Business Machines Corporation | Built-in self-test for logic circuitry at memory array output |
| US5574733A (en) | 1995-07-25 | 1996-11-12 | Intel Corporation | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator |
| DE19680782C2 (de) | 1995-07-26 | 2002-11-21 | Advantest Corp | Hochgeschwindigkeits- Mustergenerierungsverfahren und unter Verwendung dieses Verfahrens arbeitender Hochgeschwindigkeits-Mustergenerator |
| US5831992A (en) | 1995-08-17 | 1998-11-03 | Northern Telecom Limited | Methods and apparatus for fault diagnosis in self-testable systems |
| FR2738972B1 (fr) | 1995-09-15 | 1997-11-28 | Thomson Multimedia Sa | Procede de mise en gage de donnees pour un protocole d'echange de donnees securise |
| US6055658A (en) * | 1995-10-02 | 2000-04-25 | International Business Machines Corporation | Apparatus and method for testing high speed components using low speed test apparatus |
| US5680543A (en) * | 1995-10-20 | 1997-10-21 | Lucent Technologies Inc. | Method and apparatus for built-in self-test with multiple clock circuits |
| US5614838A (en) * | 1995-11-03 | 1997-03-25 | International Business Machines Corporation | Reduced power apparatus and method for testing high speed components |
| US5867507A (en) * | 1995-12-12 | 1999-02-02 | International Business Machines Corporation | Testable programmable gate array and associated LSSD/deterministic test methodology |
| JP3512939B2 (ja) | 1996-03-12 | 2004-03-31 | 株式会社ルネサステクノロジ | 疑似乱数発生回路及び双方向シフトレジスタ |
| DE69613560T2 (de) | 1996-04-30 | 2002-03-14 | Agilent Technologies Inc | Ein Prüfgerät für elektronische Schaltkreise oder Platinen mit komprimierten Datenfolgen |
| US5790562A (en) | 1996-05-06 | 1998-08-04 | General Motors Corporation | Circuit with built-in test and method thereof |
| US5668817A (en) * | 1996-07-11 | 1997-09-16 | Northern Telecom Limited | Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths |
| JPH1056361A (ja) | 1996-08-07 | 1998-02-24 | Matsushita Electric Ind Co Ltd | 疑似雑音系列発生器 |
| US5717701A (en) | 1996-08-13 | 1998-02-10 | International Business Machines Corporation | Apparatus and method for testing interconnections between semiconductor devices |
| US5812561A (en) * | 1996-09-03 | 1998-09-22 | Motorola, Inc. | Scan based testing of an integrated circuit for compliance with timing specifications |
| US5790626A (en) | 1996-09-10 | 1998-08-04 | Hewlett-Packard Company | Bi-directional linear feedback shift register |
| US5991909A (en) | 1996-10-15 | 1999-11-23 | Mentor Graphics Corporation | Parallel decompressor and related methods and apparatuses |
| KR100206128B1 (ko) * | 1996-10-21 | 1999-07-01 | 윤종용 | 선형 궤환 쉬프트레지스터, 다중 입력기호 레지스터 및 이들을 이용한 내장 자기 진단회로 |
| US5694402A (en) | 1996-10-22 | 1997-12-02 | Texas Instruments Incorporated | System and method for structurally testing integrated circuit devices |
| US5701308A (en) | 1996-10-29 | 1997-12-23 | Lockheed Martin Corporation | Fast bist architecture with flexible standard interface |
| US5905986A (en) | 1997-01-07 | 1999-05-18 | Hewlett-Packard Company | Highly compressible representation of test pattern data |
| US5991898A (en) | 1997-03-10 | 1999-11-23 | Mentor Graphics Corporation | Arithmetic built-in self test of multiple scan-based integrated circuits |
| US6199182B1 (en) * | 1997-03-27 | 2001-03-06 | Texas Instruments Incorporated | Probeless testing of pad buffers on wafer |
| US5968194A (en) * | 1997-03-31 | 1999-10-19 | Intel Corporation | Method for application of weighted random patterns to partial scan designs |
| US6026508A (en) * | 1997-04-22 | 2000-02-15 | International Business Machines Corporation | Storage sub-system compression and dataflow chip offering excellent data integrity |
| US6061818A (en) * | 1997-05-08 | 2000-05-09 | The Board Of Trustees Of The Leland Stanford Junior University | Altering bit sequences to contain predetermined patterns |
| US6097889A (en) | 1997-06-23 | 2000-08-01 | Motorola, Inc. | Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals |
| JPH1130646A (ja) | 1997-07-10 | 1999-02-02 | Nec Eng Ltd | 半導体集積回路及びそれに含まれるテスト回路 |
| US5883906A (en) * | 1997-08-15 | 1999-03-16 | Advantest Corp. | Pattern data compression and decompression for semiconductor test system |
| KR19990018125A (ko) | 1997-08-26 | 1999-03-15 | 윤종용 | Ic칩 검사용 테스터데이타 압축방법과 그 압축장치 및 ic칩용 테스터장치와 그 테스터방법 |
| US5983380A (en) * | 1997-09-16 | 1999-11-09 | International Business Machines Corporation | Weighted random pattern built-in self-test |
| DE59813158D1 (de) * | 1997-09-18 | 2005-12-08 | Infineon Technologies Ag | Verfahren zum Testen einer elektronischen Schaltung |
| US6272653B1 (en) * | 1997-11-14 | 2001-08-07 | Intrinsity, Inc. | Method and apparatus for built-in self-test of logic circuitry |
| US6198285B1 (en) | 1997-11-28 | 2001-03-06 | Hitachi Medical Corporation | In-room MRI display terminal and remote control system |
| CA2226061C (en) * | 1997-12-31 | 2002-05-28 | Logicvision, Inc. | Method and apparatus for controlling power level during bist |
| US6014763A (en) * | 1998-01-15 | 2000-01-11 | International Business Machines Corporation | At-speed scan testing |
| US6148425A (en) | 1998-02-12 | 2000-11-14 | Lucent Technologies Inc. | Bist architecture for detecting path-delay faults in a sequential circuit |
| US6158032A (en) | 1998-03-27 | 2000-12-05 | International Business Machines Corporation | Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof |
| US6141669A (en) | 1998-05-06 | 2000-10-31 | Nortel Networks Corporation | Pseudorandom binary sequence block shifter |
| US6178532B1 (en) * | 1998-06-11 | 2001-01-23 | Micron Technology, Inc. | On-chip circuit and method for testing memory devices |
| US6256759B1 (en) * | 1998-06-15 | 2001-07-03 | Agere Systems Inc. | Hybrid algorithm for test point selection for scan-based BIST |
| US6100716A (en) * | 1998-09-17 | 2000-08-08 | Nortel Networks Corporation | Voltage excursion detection apparatus |
| US6256760B1 (en) * | 1998-11-13 | 2001-07-03 | Nortel Networks Limited | Automatic test equipment scan test enhancement |
| US6286119B1 (en) * | 1998-12-22 | 2001-09-04 | Nortel Networks Limited | Delay fault testing with IEEE 1149.1 |
| US6240432B1 (en) * | 1998-12-28 | 2001-05-29 | Vanguard International Semiconductor Corporation | Enhanced random number generator |
| GB9900432D0 (en) | 1999-01-08 | 1999-02-24 | Xilinx Inc | Linear feedback shift register in a progammable gate array |
| US6467058B1 (en) | 1999-01-20 | 2002-10-15 | Nec Usa, Inc. | Segmented compaction with pruning and critical fault elimination |
| US6327685B1 (en) | 1999-05-12 | 2001-12-04 | International Business Machines Corporation | Logic built-in self test |
| US6590929B1 (en) * | 1999-06-08 | 2003-07-08 | International Business Machines Corporation | Method and system for run-time logic verification of operations in digital systems |
| US6463560B1 (en) * | 1999-06-23 | 2002-10-08 | Agere Systems Guardian Corp. | Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits |
| US6385750B1 (en) | 1999-09-01 | 2002-05-07 | Synopsys, Inc. | Method and system for controlling test data volume in deterministic test pattern generation |
| US6694466B1 (en) * | 1999-10-27 | 2004-02-17 | Agere Systems Inc. | Method and system for improving the test quality for scan-based BIST using a general test application scheme |
| US7493540B1 (en) * | 1999-11-23 | 2009-02-17 | Jansuz Rajski | Continuous application and decompression of test patterns to a circuit-under-test |
| US6327687B1 (en) * | 1999-11-23 | 2001-12-04 | Janusz Rajski | Test pattern compression for an integrated circuit test environment |
| US6874109B1 (en) * | 1999-11-23 | 2005-03-29 | Janusz Rajski | Phase shifter with reduced linear dependency |
| WO2001039254A2 (en) * | 1999-11-23 | 2001-05-31 | Mentor Graphics Corporation | Continuous application and decompression of test patterns to a circuit-under-test |
| US6557129B1 (en) * | 1999-11-23 | 2003-04-29 | Janusz Rajski | Method and apparatus for selectively compacting test responses |
| US6684358B1 (en) * | 1999-11-23 | 2004-01-27 | Janusz Rajski | Decompressor/PRPG for applying pseudo-random and deterministic test patterns |
| EP1475643B1 (de) | 1999-11-23 | 2006-09-20 | Mentor Graphics Corporation | Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen |
| US6353842B1 (en) * | 1999-11-23 | 2002-03-05 | Janusz Rajski | Method for synthesizing linear finite state machines |
| DE60108993T2 (de) | 2000-03-09 | 2005-07-21 | Texas Instruments Inc., Dallas | Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch |
| US6611933B1 (en) * | 2000-04-12 | 2003-08-26 | International Business Machines Corporation | Real-time decoder for scan test patterns |
| US6300885B1 (en) | 2000-04-14 | 2001-10-09 | International Business Machines Corporation | Dual aldc decompressors inside printer asic |
| US6510398B1 (en) * | 2000-06-22 | 2003-01-21 | Intel Corporation | Constrained signature-based test |
| US6618826B1 (en) | 2000-10-26 | 2003-09-09 | Cadence Design Systems, Inc. | Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs |
| JP4228061B2 (ja) | 2000-12-07 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 集積回路の試験装置および試験方法 |
| US7234092B2 (en) * | 2002-06-11 | 2007-06-19 | On-Chip Technologies, Inc. | Variable clocked scan test circuitry and method |
| JP4278940B2 (ja) * | 2002-09-09 | 2009-06-17 | 株式会社 液晶先端技術開発センター | 結晶化装置および結晶化方法 |
| US7200784B2 (en) * | 2003-01-24 | 2007-04-03 | On-Chip Technologies, Inc. | Accelerated scan circuitry and method for reducing scan test data volume and execution time |
| US20060038485A1 (en) * | 2004-08-18 | 2006-02-23 | Harvatek Corporation | Laminated light-emitting diode display device and manufacturing method thereof |
| US7484151B2 (en) * | 2005-10-03 | 2009-01-27 | Nec Laboratories America, Inc. | Method and apparatus for testing logic circuit designs |
-
2000
- 2000-07-20 US US09/619,985 patent/US6327687B1/en not_active Expired - Lifetime
- 2000-11-15 EP EP00978684A patent/EP1236111B1/de not_active Expired - Lifetime
- 2000-11-15 WO PCT/US2000/031377 patent/WO2001038981A1/en active IP Right Grant
- 2000-11-15 AT AT04017880T patent/ATE340363T1/de not_active IP Right Cessation
- 2000-11-15 AT AT00978684T patent/ATE289094T1/de not_active IP Right Cessation
- 2000-11-15 DE DE60018101T patent/DE60018101T2/de not_active Expired - Lifetime
- 2000-11-15 DE DE60030896T patent/DE60030896T2/de not_active Expired - Lifetime
- 2000-11-15 JP JP2001540467A patent/JP3920640B2/ja not_active Expired - Fee Related
-
2001
- 2001-09-04 US US09/947,160 patent/US6543020B2/en not_active Expired - Lifetime
-
2003
- 2003-01-23 HK HK03100614.3A patent/HK1049215A1/zh unknown
- 2003-01-31 US US10/355,941 patent/US7111209B2/en not_active Expired - Lifetime
-
2006
- 2006-09-18 US US11/523,111 patent/US7509546B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| ATE289094T1 (de) | 2005-02-15 |
| JP2003515809A (ja) | 2003-05-07 |
| US7509546B2 (en) | 2009-03-24 |
| EP1236111B1 (de) | 2005-02-09 |
| ATE340363T1 (de) | 2006-10-15 |
| US6543020B2 (en) | 2003-04-01 |
| DE60018101T2 (de) | 2006-01-12 |
| DE60030896D1 (de) | 2006-11-02 |
| US6327687B1 (en) | 2001-12-04 |
| US20090259900A1 (en) | 2009-10-15 |
| EP1236111A1 (de) | 2002-09-04 |
| EP1236111A4 (de) | 2003-09-17 |
| US20020053057A1 (en) | 2002-05-02 |
| US20070016836A1 (en) | 2007-01-18 |
| DE60030896T2 (de) | 2007-09-20 |
| US7111209B2 (en) | 2006-09-19 |
| US20030131298A1 (en) | 2003-07-10 |
| JP3920640B2 (ja) | 2007-05-30 |
| US7900104B2 (en) | 2011-03-01 |
| HK1049215A1 (zh) | 2003-05-02 |
| WO2001038981A1 (en) | 2001-05-31 |
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