DE60021129D1 - Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung - Google Patents

Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung

Info

Publication number
DE60021129D1
DE60021129D1 DE60021129T DE60021129T DE60021129D1 DE 60021129 D1 DE60021129 D1 DE 60021129D1 DE 60021129 T DE60021129 T DE 60021129T DE 60021129 T DE60021129 T DE 60021129T DE 60021129 D1 DE60021129 D1 DE 60021129D1
Authority
DE
Germany
Prior art keywords
semiconductor device
bus line
output signal
logical output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60021129T
Other languages
English (en)
Other versions
DE60021129T2 (de
Inventor
Yoshiharu Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11024890A external-priority patent/JP2000221226A/ja
Priority claimed from JP03791099A external-priority patent/JP3950247B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60021129D1 publication Critical patent/DE60021129D1/de
Publication of DE60021129T2 publication Critical patent/DE60021129T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
    • G09B19/00—Teaching not covered by other main groups of this subclass
    • G09B19/12—Clock-reading
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63H—TOYS, e.g. TOPS, DOLLS, HOOPS OR BUILDING BLOCKS
    • A63H33/00—Other toys
    • A63H33/30—Imitations of miscellaneous apparatus not otherwise provided for, e.g. telephones, weighing-machines, cash-registers
    • A63H33/3066—Watches or clocks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
DE60021129T 1999-02-02 2000-01-31 Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung Expired - Fee Related DE60021129T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP11024890A JP2000221226A (ja) 1999-02-02 1999-02-02 電子機器の試験方法、電子機器、及び、半導体装置
JP2489099 1999-02-02
JP3791099 1999-02-16
JP03791099A JP3950247B2 (ja) 1999-02-16 1999-02-16 半導体集積回路

Publications (2)

Publication Number Publication Date
DE60021129D1 true DE60021129D1 (de) 2005-08-11
DE60021129T2 DE60021129T2 (de) 2006-05-18

Family

ID=26362467

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60021129T Expired - Fee Related DE60021129T2 (de) 1999-02-02 2000-01-31 Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung

Country Status (5)

Country Link
US (2) US7028235B1 (de)
EP (2) EP1026696B1 (de)
KR (1) KR100555170B1 (de)
DE (1) DE60021129T2 (de)
TW (1) TW527491B (de)

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US20070046308A1 (en) * 2005-08-26 2007-03-01 Ronald Baker Test modes for a semiconductor integrated circuit device
JP4791533B2 (ja) * 2006-03-16 2011-10-12 パナソニック株式会社 端末装置
KR100907930B1 (ko) * 2007-07-03 2009-07-16 주식회사 하이닉스반도체 테스트 시간을 줄일 수 있는 반도체 메모리 장치
US20090112548A1 (en) * 2007-10-30 2009-04-30 Conner George W A method for testing in a reconfigurable tester
US20090113245A1 (en) 2007-10-30 2009-04-30 Teradyne, Inc. Protocol aware digital channel apparatus
JP5241288B2 (ja) * 2008-03-31 2013-07-17 ルネサスエレクトロニクス株式会社 半導体装置及びその動作モード設定方法
KR101026244B1 (ko) * 2008-03-31 2011-03-31 르네사스 일렉트로닉스 가부시키가이샤 동작 모드를 스위칭할 수 있는 반도체 장치 및 이에 대한 동작 모드 세팅 방법
JP5599560B2 (ja) * 2008-11-27 2014-10-01 富士通セミコンダクター株式会社 半導体メモリ
JP5416200B2 (ja) 2009-02-27 2014-02-12 株式会社日立製作所 半導体装置
JP2010203898A (ja) * 2009-03-03 2010-09-16 Renesas Electronics Corp 半導体装置のテスト回路、半導体装置及びその製造方法
JP5635924B2 (ja) 2011-02-22 2014-12-03 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその試験方法
JP6018380B2 (ja) * 2011-12-27 2016-11-02 川崎重工業株式会社 スマートグリッドシステムのグリッドコントローラ、それを備えたスマートグリッドシステムおよびその制御方法
KR102077072B1 (ko) * 2013-07-05 2020-02-14 에스케이하이닉스 주식회사 병렬 테스트 장치 및 방법
JP2018017605A (ja) * 2016-07-28 2018-02-01 ルネサスエレクトロニクス株式会社 半導体装置及びそれを備えた半導体システム
JP2021143982A (ja) 2020-03-13 2021-09-24 株式会社東芝 方法、磁気ディスク装置の検査方法、および電子部品

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Also Published As

Publication number Publication date
KR100555170B1 (ko) 2006-03-03
US20050270859A1 (en) 2005-12-08
KR20000071321A (ko) 2000-11-25
EP1026696A2 (de) 2000-08-09
EP1026696B1 (de) 2005-07-06
EP1515345A1 (de) 2005-03-16
EP1026696A3 (de) 2001-04-04
US7028235B1 (en) 2006-04-11
TW527491B (en) 2003-04-11
US7251766B2 (en) 2007-07-31
DE60021129T2 (de) 2006-05-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee