DE60034756D1 - Flip-Chip-Montage eines IC auf eine Leiterplatte - Google Patents

Flip-Chip-Montage eines IC auf eine Leiterplatte

Info

Publication number
DE60034756D1
DE60034756D1 DE60034756T DE60034756T DE60034756D1 DE 60034756 D1 DE60034756 D1 DE 60034756D1 DE 60034756 T DE60034756 T DE 60034756T DE 60034756 T DE60034756 T DE 60034756T DE 60034756 D1 DE60034756 D1 DE 60034756D1
Authority
DE
Germany
Prior art keywords
flip
circuit board
printed circuit
chip mounting
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60034756T
Other languages
English (en)
Other versions
DE60034756T2 (de
Inventor
Wakahiro Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Application granted granted Critical
Publication of DE60034756D1 publication Critical patent/DE60034756D1/de
Publication of DE60034756T2 publication Critical patent/DE60034756T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
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    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
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    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189Pressing leads, bumps or a die through an insulating layer
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
DE60034756T 1999-11-24 2000-11-23 Flip-Chip-Montage eines IC auf eine Leiterplatte Expired - Lifetime DE60034756T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP33340999A JP3451373B2 (ja) 1999-11-24 1999-11-24 電磁波読み取り可能なデータキャリアの製造方法
JP33340999 1999-11-24

Publications (2)

Publication Number Publication Date
DE60034756D1 true DE60034756D1 (de) 2007-06-21
DE60034756T2 DE60034756T2 (de) 2008-01-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE60034756T Expired - Lifetime DE60034756T2 (de) 1999-11-24 2000-11-23 Flip-Chip-Montage eines IC auf eine Leiterplatte

Country Status (7)

Country Link
US (2) US6406990B1 (de)
EP (2) EP1801867A3 (de)
JP (1) JP3451373B2 (de)
KR (2) KR20010070230A (de)
CN (2) CN100473255C (de)
DE (1) DE60034756T2 (de)
SG (1) SG114482A1 (de)

Families Citing this family (163)

* Cited by examiner, † Cited by third party
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EP1104017A2 (de) 2001-05-30
CN1300180A (zh) 2001-06-20
KR20030081215A (ko) 2003-10-17
CN1300180B (zh) 2010-09-29
EP1104017B1 (de) 2007-05-09
US6664645B2 (en) 2003-12-16
CN100473255C (zh) 2009-03-25
DE60034756T2 (de) 2008-01-31
CN1529544A (zh) 2004-09-15
EP1801867A2 (de) 2007-06-27
KR20010070230A (ko) 2001-07-25
EP1104017A3 (de) 2003-11-12
EP1801867A3 (de) 2007-08-29
US6406990B1 (en) 2002-06-18
JP3451373B2 (ja) 2003-09-29
JP2001156110A (ja) 2001-06-08
US20020115278A1 (en) 2002-08-22
KR100419466B1 (ko) 2004-02-19

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