DE60036286D1 - Oberflächenbehandlung eines soi substrats mittels eines epitaxie-verfahrens - Google Patents

Oberflächenbehandlung eines soi substrats mittels eines epitaxie-verfahrens

Info

Publication number
DE60036286D1
DE60036286D1 DE60036286T DE60036286T DE60036286D1 DE 60036286 D1 DE60036286 D1 DE 60036286D1 DE 60036286 T DE60036286 T DE 60036286T DE 60036286 T DE60036286 T DE 60036286T DE 60036286 D1 DE60036286 D1 DE 60036286D1
Authority
DE
Germany
Prior art keywords
hydrogen
epitaxis
procedure
surface treatment
soi substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60036286T
Other languages
English (en)
Other versions
DE60036286T2 (de
Inventor
Sien G Kang
Igor J Malik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Genesis Corp
Original Assignee
Silicon Genesis Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Genesis Corp filed Critical Silicon Genesis Corp
Application granted granted Critical
Publication of DE60036286D1 publication Critical patent/DE60036286D1/de
Publication of DE60036286T2 publication Critical patent/DE60036286T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/967Semiconductor on specified insulator
DE60036286T 1999-04-21 2000-04-20 Oberflächenbehandlung eines soi substrats mittels eines epitaxie-verfahrens Expired - Lifetime DE60036286T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13042399P 1999-04-21 1999-04-21
US130423P 1999-04-21
US09/399,985 US6287941B1 (en) 1999-04-21 1999-09-20 Surface finishing of SOI substrates using an EPI process
US399985 1999-09-20
PCT/US2000/010872 WO2000063954A1 (en) 1999-04-21 2000-04-20 Surface finishing of soi substrates using an epi process

Publications (2)

Publication Number Publication Date
DE60036286D1 true DE60036286D1 (de) 2007-10-18
DE60036286T2 DE60036286T2 (de) 2008-06-05

Family

ID=26828477

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60036286T Expired - Lifetime DE60036286T2 (de) 1999-04-21 2000-04-20 Oberflächenbehandlung eines soi substrats mittels eines epitaxie-verfahrens

Country Status (8)

Country Link
US (3) US6287941B1 (de)
EP (2) EP1887616A3 (de)
JP (1) JP2002542622A (de)
KR (2) KR100709689B1 (de)
AT (1) ATE372590T1 (de)
AU (1) AU4483300A (de)
DE (1) DE60036286T2 (de)
WO (1) WO2000063954A1 (de)

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WO2000063954A1 (en) 2000-10-26
KR100709689B1 (ko) 2007-04-19
KR20020007377A (ko) 2002-01-26
US7253081B2 (en) 2007-08-07
US6287941B1 (en) 2001-09-11
US20070259526A1 (en) 2007-11-08
AU4483300A (en) 2000-11-02
EP1887616A3 (de) 2008-05-28
DE60036286T2 (de) 2008-06-05
EP1194949B1 (de) 2007-09-05
EP1194949A1 (de) 2002-04-10
US20020022344A1 (en) 2002-02-21
KR20060126629A (ko) 2006-12-07
EP1887616A2 (de) 2008-02-13
JP2002542622A (ja) 2002-12-10
ATE372590T1 (de) 2007-09-15
EP1194949A4 (de) 2003-07-30

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